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Part Number: MC9S12A256
Description: This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and d...
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MC9S12A256
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DataSheet
General Description
MC9S12A256 General Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block User Guides of the individual IP blocks on the device.
MC9S12A256 Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
| Num | Rating | Symbol | Min | Max | Unit |
| 1 | I/O, Regulator and Analog Supply Voltage | VDD5 | -0.3 | 6.0 | V |
| 2 | Digital Logic Supply Voltage 2 | VDD | -0.3 | 3.0 | V |
| 3 | PLL Supply Voltage 2 | VDDPLL | -0.3 | 3.0 | V |
| 4 | Voltage difference VDDX to VDDR and VDDA | DVDDX | -0.3 | 0.3 | V |
| 5 | Voltage difference VSSX to VSSR and VSSA | DVSSX | -0.3 | 0.3 | V |
| 6 | Digital I/O Input Voltage | VIN | -0.3 | 6.0 | V |
| 7 | Analog Reference | VRH, VRL | -0.3 | 6.0 | V |
| 8 | XFC, EXTAL, XTAL inputs | VILV | -0.3 | 3.0 | V |
| 9 | TEST input | VTEST | -0.3 | 10.0 | V |
| 10 | Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 |
ID | -25 | +25 | mA |
| 11 | Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 |
IDL | -25 | +25 | mA |
| 12 | Instantaneous Maximum Current Single pin limit for TEST 5 |
IDT | -0.25 | 0 | mA |
| 13 | Storage Temperature Range | Tstg | 65 | 155 |
MC9S12A256 Features
• HCS12 Core
16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer's model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
MEBI (Multiplexed External Bus Interface)
MMC (Module Mapping Control)
INT (Interrupt control)
BKP (Breakpoints)
BDM (Background Debug Mode)
• CRG
Low current Colpitts or Pierce oscillator
PLL
COP watchdog
Real time interrupt
Clock Monitor
• 8-bit and 4-bit ports with interrupt functionality
Digital filtering
Programmable rising or falling edge trigger
• Memory
256K Flash EEPROM
4K byte EEPROM
12K byte RAM
• Two 8-channel Analog-to-Digital Converters
10-bit resolution
External conversion trigger capability
• Three 1M bit per second, CAN 2.0 A, B software compatible modules
Five receive and three transmit buffers
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
Four separate interrupt channels for Rx, Tx, error and wake-up
Low-pass filter wake-up function
Loop-back for self test operation
• Enhanced Capture Timer
16-bit main counter with 7-bit prescaler
8 programmable input capture or output compare channels
Four 8-bit or two 16-bit pulse accumulators
• 8 PWM channels
Programmable period and duty cycle
8-bit 8-channel or 16-bit 4-channel
Separate control for each pulse width and duty cycle
Center-aligned or left-aligned outputs
Programmable clock select logic with a wide range of frequencies
Fast emergency shutdown input
Usable as interrupt inputs
• Serial interfaces
Two asynchronous Serial Communications Interfaces (SCI)
Three Synchronous Serial Peripheral Interface (SPI)
• Byte Data Link Controller (BDLC)
SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications
• Inter-IC Bus (IIC)
Compatible with I2C Bus standard
Multi-master operation
Software programmable for one of 256 different serial clock frequencies
• 112-Pin LQFP package
I/O lines with 5V input and drive capability
5V A/D converter inputs
Operation at 50MHz equivalent to 25MHz Bus Speed
Development support
Single-wire background debug™ mode (BDM)
On-chip hardware breakpoints
16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer's model identical to M68HC11
iii. Instruction queue
iv. Enhanced indexed addressing
MEBI (Multiplexed External Bus Interface)
MMC (Module Mapping Control)
INT (Interrupt control)
BKP (Breakpoints)
BDM (Background Debug Mode)
• CRG
Low current Colpitts or Pierce oscillator
PLL
COP watchdog
Real time interrupt
Clock Monitor
• 8-bit and 4-bit ports with interrupt functionality
Digital filtering
Programmable rising or falling edge trigger
• Memory
256K Flash EEPROM
4K byte EEPROM
12K byte RAM
• Two 8-channel Analog-to-Digital Converters
10-bit resolution
External conversion trigger capability
• Three 1M bit per second, CAN 2.0 A, B software compatible modules
Five receive and three transmit buffers
Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
Four separate interrupt channels for Rx, Tx, error and wake-up
Low-pass filter wake-up function
Loop-back for self test operation
• Enhanced Capture Timer
16-bit main counter with 7-bit prescaler
8 programmable input capture or output compare channels
Four 8-bit or two 16-bit pulse accumulators
• 8 PWM channels
Programmable period and duty cycle
8-bit 8-channel or 16-bit 4-channel
Separate control for each pulse width and duty cycle
Center-aligned or left-aligned outputs
Programmable clock select logic with a wide range of frequencies
Fast emergency shutdown input
Usable as interrupt inputs
• Serial interfaces
Two asynchronous Serial Communications Interfaces (SCI)
Three Synchronous Serial Peripheral Interface (SPI)
• Byte Data Link Controller (BDLC)
SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications
• Inter-IC Bus (IIC)
Compatible with I2C Bus standard
Multi-master operation
Software programmable for one of 256 different serial clock frequencies
• 112-Pin LQFP package
I/O lines with 5V input and drive capability
5V A/D converter inputs
Operation at 50MHz equivalent to 25MHz Bus Speed
Development support
Single-wire background debug™ mode (BDM)
On-chip hardware breakpoints
MC9S12A256 Connection Diagram
MC9S12A256
PDF/DataSheet Download
- Datasheet: MC9S12A256
- File Size: 2127181 KB
- Manufacturer: MOTOROLA [Motorola, Inc]
- Click here to Download
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