MC9S12DB Features
• 16-bit CPU12
- Upward compatible with M68HC11 instruction set
- Interrupt stacking and programmer's model identical to M68HC11
- 20-bit ALU
- Instruction queue
- Enhanced indexed addressing
• Multiplexed bus
- Single chip or expanded
- 16 address/16 data wide or 16 address/8 data narrow modes
- External address space 1MByte for Data and Program space (112 pin package only)
• Wake-up interrupt inputs depending on the package option
- 8-bit port H
- 4-bit port J
- 8-bit port shared with PWM/SPI
• Memory options
- 32K, 128K Byte Flash EEPROM
- 1K, 2K Byte EEPROM
- 2K, 8K Byte RAM
• One or Two Analog-to-Digital Converters
- 1 or 2 times 8-channels, 10-bit resolution depending on the package option
- External conversion trigger capability
• Up to two 1M bit per second, CAN 2.0 A, B software compatible modules
- Five receive and three transmit buffers
- Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
- Four separate interrupt channels for Rx, Tx, error and wake-up
- Low-pass filter wake-up function
- Loop-back for self test operation
• Enhanced Capture Timer (ECT)
- 16-bit main counter with 7-bit prescaler
- 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer
- Input capture filters and buffers, three successive captures on four channels, or two captures on four
channels with a capture/compare selectable on the remaining four
- Four 8-bit or two 16-bit pulse accumulators
- 16-bit modulus down-counter with 4-bit prescaler
- Four user-selectable delay counters for signal filtering
• 7 or 8 PWM channels with programmable period and duty cycle,
- 8-bit 4-channel or 16-bit 2-channel (80 Pin Version)
- 8-bit 8-channel or 16-bit 4-channel (112 Pin Version)
- Separate control for each pulse width and duty cycle
- Center- or left-aligned outputs
- Programmable clock select logic with a wide range of frequencies
• Serial interfaces
- Two asynchronous serial communications interfaces (SCI)
- Up to two synchronous serial peripheral interfaces (SPI)
• Byteflight
- 10MBit/s serial protocoll
• SIM (System Integration Module)
- CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset)
- MEBI (multiplexed external bus interface)
- MMC (memory map and interface)
- INT (interrupt control)
- BKP (breakpoints)
- BDM (background debug mode)
• Clock generation
- Phase-locked loop clock frequency multiplier
- Limp home mode in absence of external clock
- Slow mode divider
- Low power 0.5 to 40 MHz crystal oscillator reference clock
• Operating frequency
- 50MHz equivalent to 25MHz Bus Speed for single chip
- 40MHz equivalent to 20MHz Bus Speed in expanded bus modes
• Internal 5V to 2.5V Regulator
• 112-Pin LQFP or 80-Pin QFP package
- I/O lines with 5V input and drive capability
- 5VA/D converter inputs
- Dual supply - 5V for I/O and A/D, 2.5V logic
• Development support
- Single-wire background debug™ mode (BDM)
- On-chip hardware breakpoints
MC9S12DB Connection Diagram
Map list: ABCDEFGHIJKLMNOPQRSTUVWXYZ 0123456789All