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Part Number: MCF5275EC
Description: The MCF5275 family is a highly integrated Table of Contents implementation of the ColdFire® family of reducedin...
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MCF5275EC
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General Description
MCF5275EC General Description
The MCF5275 family is a highly integrated Table of Contents implementation of the ColdFire® family of reduced
instruction set computing (RISC) microprocessors. This document describes pertinent features and functions
characteristics of the MCF5275 family. The MCF5275 family includes the MCF5275, MCF5275L, MCF5274 and MCF5274L microprocessors. The differences between these parts are summarized in Table 1. This document is written from the perspective of the MCF5275 and unless otherwise noted, the information applies also to the MCF5275L, MCF5274 and
MCF5274L.
The MCF5275 family delivers a new level of performance and integration on the popular version 2 ColdFire core with up to 159 (Dhrystone 2.1) MIPS @ 166MHz. These highly integrated microprocessors build upon the widely used peripheral mix on the popular MCF5272 ColdFire microprocessor (10/100 Mbps Ethernet MAC and USB device) by adding a second 10/100 Mbps Ethernet MAC (MCF5274 and MCF5275) and hardware encryption (MCF5275L and MCF5275). In addition, the MCF5275 family features an Enhanced Multiply Accumulate Unit (EMAC), large on-chipmemory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM memory controller.
These devices are ideal for cost-sensitive applications requiring significant control processing for file management, connectivity, data buffering, and user interface, as well as signal processing in a variety of key markets such as security, imaging, networking, gaming, and medical. This leading package of integration and high performance allows fast time to market through easy code reuse and extensive third party tool support.
To locate any published errata or updates for this document, refer to the ColdFire products website at
http://www.freescale.com.
MCF5275EC Maximum Ratings
|
Rating |
Symbol |
Value |
Unit |
|
Core Supply Voltage |
VDD |
0.5 to +2.0 |
V |
|
I/O Pad Supply Voltage (3.3V) |
O VDD |
0.3 to +4.0 |
V |
|
Memory Interface SSTL 2.5V Pad Supply Voltage |
SD VDD |
0.3 to + 2.8 |
V |
|
Memory Interface SSTL 3.3V Pad Supply Voltage |
SD VDD |
0.3 to +4.0 |
V |
|
Clock Synthesizer Supply Voltage |
VDDPLL |
0.3 to +4.0 |
V |
|
Digital Input Voltage 3 |
VIN |
0.3 to +4.0 |
V |
|
EXTAL pin voltage |
VEXTAL |
0 to 3.3 |
V |
|
XTAL pin voltage |
VXTAL |
0 to 3.3 |
V |
NOTES:
1 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device.
2 This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or O VDD).
3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
4 All functional non-supply pins are internally clamped to VSS and O VDD.
5 Power supply must maintain regulation within operating O VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > O VDD) is greater than IDD, the injection current may flow out of O VDD and could result in external power supply going out of regulation. Insure external O VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions.
MCF5275EC Features
• ColdFire version 2 variable-length RISC processor
- Static operation
- 32-bit address and data path on-chip
- 166/133 MHz processor core and 83/66.5 MHz bus frequency
- Sixteen general-purpose 32-bit data and address registers
- Enhanced multiply accumulate unit (eMAC) for DSP and fast multiply operations
• System debug support
- Real time trace for determining dynamic execution path while in emulator mode
- Background debug mode (BDM) for debug features while halted
- Real time debug support, with two user visible hardware breakpoint registers (PC and address
with optional data) that can be configured into a 1- or 2-level trigger
• On chip memories
- 16 Kbyte cache, configurable as I-cache or I-cache and D-cache
- 64 Kbyte dual-ported SRAM on CPU internal bus with standby power supply support
• Power management
- Fully static operation with processor sleep and whole chip stop modes
- Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
• Two Fast Ethernet Media Access Controllers (FEC MAC)
- 10 base T capability, half or full duplex
- 100 base T capability, half or full duplex throughput
- On chip transmit and receive FIFOs
- Built-in DMA controller
- Memory-based flexible descriptor rings
- Media independent interface (MII)
• USB Device Module
- Supports full-speed 12-Mbps and low-speed 1.5-Mbps USB devices
- Full compliance with the Universal Serial Bus Specification, Revision 2.0
- Automatic hardware processing of USB standard device requests
- Supports external USB transceiver
- Protocol control and administration for up to four endpoints (programmable types)
- One FIFO RAM per endpoint (2-Kbyte total)
- Dedicated 1-Kbyte descriptor RAM, accessible from the Slave bus
- Remote wake-up
• Hardware cryptography accelerator (optional)
- Random number generator
- DES/3DES/AES block cipher engine
- MD5/SHA-1/HMAC accelerator
• Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs)
- Serial communication channel
- 16-bit divider for clock generation
- Internal channel control logic
- Interrupt control logic
- Maskable interrupts
- DMA support
- Programmable clock-rate generator
- Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
- Up to 2 stop bits in 1/16 increments
- Error-detection capabilities
- Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines
- Transmit and receive FIFO buffers
• I2C Module
- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
- Fully compatible with industry-standard I2C bus
- Master or slave modes support multiple masters
- Automatic interrupt generation with programmable level
• Queued Serial Peripheral Interface (QSPI)
- Full-duplex, three-wire synchronous transfer
- Up to four chip selects available
- Master operation
- Programmable master bit rates
- Up to 16 preprogrammed transfers
• Four 32-bit Timers with DMA request capability
• Pulse width modulation (PWM) unit
- Four identical channels
• Software Watchdog Timer
- 16-bit counter
- Low power mode support
• Phase Locked Loop (PLL)
- Reference crystal 8 to 25 MHz
- Low power modes supported
- Separate CLKOUT and DDR_CLKOUT signals
• Four Programmable Interrupt Timers (PITs)
• Interrupt Controllers (x2)
- Support for 58 independent interrupt sources, organized as follows:
51 fully-programmable interrupt sources
7 fixed-level external interrupt sources
- Unique vector number for each interrupt source
- Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
- Support for hardware and software interrupt acknowledge (IACK) cycles
- Combinatorial path to provide wake-up from low power modes
• DMA Controller
- Four fully programmable channels
- Dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability
- Source/destination address pointers that can increment or remain constant
- 24-bit transfer counter per channel
- Auto-alignment transfers supported for efficient block movement
- Bursting and cycle steal support
- Two-bus-clock internal access
- External request pins for each channel
• External Memory Interface
- External glueless connections to 8-, 16-, and 32-bit external memory devices (e.g., SRAM, flash, ROM, etc.)
- Glueless interface to SRAM devices with or without byte strobe inputs
- Programmable wait state generator
- 16-bit external bidirectional data bus
- 24-bit address bus
- Eight chip selects
- Byte/write enables
- Ability to boot from external memories that are 8 or 16 bits wide
• DDR SDRAM controller
- Supports 16-bit wide memory devices
- Supports Dual Data Rate (DDR) SDRAM.
- Page mode support
- Programmable refresh interval timer.
- Sleep mode and self-refresh.
- Supports 16-byte (4-beat, 4-byte) critical-word-first burst transfer.
- Memory sizes from 8 Mbyte to 128 MByte (per chip select)
- 166 MHz data transfer rate (DDR)
- Two independent chip selects
• Reset
- Separate Reset In and Reset Out signals
- Six sources of reset (POR, External, Software, Watchdog, Loss of clock/lock)
- Status flag indication of source of last reset
• Chip Configurations
- System configuration during reset
- Bus Monitor, Abort Monitor
- Configurable output pad drive strength
- Unique Part Identification and Part Revision Numbers
• General Purpose I/O interface
- Up to 69 bits of general purpose I/O
- Coherent 32-bit control
- Bit manipulation supported via set/clear functions
- Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing
- Unique JTAG Part Identification and Part Revision Numbers
- Static operation
- 32-bit address and data path on-chip
- 166/133 MHz processor core and 83/66.5 MHz bus frequency
- Sixteen general-purpose 32-bit data and address registers
- Enhanced multiply accumulate unit (eMAC) for DSP and fast multiply operations
• System debug support
- Real time trace for determining dynamic execution path while in emulator mode
- Background debug mode (BDM) for debug features while halted
- Real time debug support, with two user visible hardware breakpoint registers (PC and address
with optional data) that can be configured into a 1- or 2-level trigger
• On chip memories
- 16 Kbyte cache, configurable as I-cache or I-cache and D-cache
- 64 Kbyte dual-ported SRAM on CPU internal bus with standby power supply support
• Power management
- Fully static operation with processor sleep and whole chip stop modes
- Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
• Two Fast Ethernet Media Access Controllers (FEC MAC)
- 10 base T capability, half or full duplex
- 100 base T capability, half or full duplex throughput
- On chip transmit and receive FIFOs
- Built-in DMA controller
- Memory-based flexible descriptor rings
- Media independent interface (MII)
• USB Device Module
- Supports full-speed 12-Mbps and low-speed 1.5-Mbps USB devices
- Full compliance with the Universal Serial Bus Specification, Revision 2.0
- Automatic hardware processing of USB standard device requests
- Supports external USB transceiver
- Protocol control and administration for up to four endpoints (programmable types)
- One FIFO RAM per endpoint (2-Kbyte total)
- Dedicated 1-Kbyte descriptor RAM, accessible from the Slave bus
- Remote wake-up
• Hardware cryptography accelerator (optional)
- Random number generator
- DES/3DES/AES block cipher engine
- MD5/SHA-1/HMAC accelerator
• Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs)
- Serial communication channel
- 16-bit divider for clock generation
- Internal channel control logic
- Interrupt control logic
- Maskable interrupts
- DMA support
- Programmable clock-rate generator
- Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
- Up to 2 stop bits in 1/16 increments
- Error-detection capabilities
- Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines
- Transmit and receive FIFO buffers
• I2C Module
- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
- Fully compatible with industry-standard I2C bus
- Master or slave modes support multiple masters
- Automatic interrupt generation with programmable level
• Queued Serial Peripheral Interface (QSPI)
- Full-duplex, three-wire synchronous transfer
- Up to four chip selects available
- Master operation
- Programmable master bit rates
- Up to 16 preprogrammed transfers
• Four 32-bit Timers with DMA request capability
• Pulse width modulation (PWM) unit
- Four identical channels
• Software Watchdog Timer
- 16-bit counter
- Low power mode support
• Phase Locked Loop (PLL)
- Reference crystal 8 to 25 MHz
- Low power modes supported
- Separate CLKOUT and DDR_CLKOUT signals
• Four Programmable Interrupt Timers (PITs)
• Interrupt Controllers (x2)
- Support for 58 independent interrupt sources, organized as follows:
51 fully-programmable interrupt sources
7 fixed-level external interrupt sources
- Unique vector number for each interrupt source
- Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
- Support for hardware and software interrupt acknowledge (IACK) cycles
- Combinatorial path to provide wake-up from low power modes
• DMA Controller
- Four fully programmable channels
- Dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability
- Source/destination address pointers that can increment or remain constant
- 24-bit transfer counter per channel
- Auto-alignment transfers supported for efficient block movement
- Bursting and cycle steal support
- Two-bus-clock internal access
- External request pins for each channel
• External Memory Interface
- External glueless connections to 8-, 16-, and 32-bit external memory devices (e.g., SRAM, flash, ROM, etc.)
- Glueless interface to SRAM devices with or without byte strobe inputs
- Programmable wait state generator
- 16-bit external bidirectional data bus
- 24-bit address bus
- Eight chip selects
- Byte/write enables
- Ability to boot from external memories that are 8 or 16 bits wide
• DDR SDRAM controller
- Supports 16-bit wide memory devices
- Supports Dual Data Rate (DDR) SDRAM.
- Page mode support
- Programmable refresh interval timer.
- Sleep mode and self-refresh.
- Supports 16-byte (4-beat, 4-byte) critical-word-first burst transfer.
- Memory sizes from 8 Mbyte to 128 MByte (per chip select)
- 166 MHz data transfer rate (DDR)
- Two independent chip selects
• Reset
- Separate Reset In and Reset Out signals
- Six sources of reset (POR, External, Software, Watchdog, Loss of clock/lock)
- Status flag indication of source of last reset
• Chip Configurations
- System configuration during reset
- Bus Monitor, Abort Monitor
- Configurable output pad drive strength
- Unique Part Identification and Part Revision Numbers
• General Purpose I/O interface
- Up to 69 bits of general purpose I/O
- Coherent 32-bit control
- Bit manipulation supported via set/clear functions
- Unused peripheral pins may be used as extra GPIO
• JTAG support for system level board testing
- Unique JTAG Part Identification and Part Revision Numbers
MCF5275EC Connection Diagram
MCF5202
PDF/DataSheet Download
- Datasheet: MCF5202
- File Size: 909005 KB
- Manufacturer: Motorola
- Click here to Download
- ·MCF5204
- Motorola
- MCF5204 ColdFire ? Integrated Microprocessor
- 30636 KB
- ·MCF5206
- MOTOROLA [Motorola, Inc]
- MCF5206 Integrated Microprocessor
- 213353 KB
- ·MCF5213EC
- 1249956 KB
- ·MCF5232
- FREESCALE [Freescale Semiconductor, Inc]
- Integrated Microprocessor Hardware Specification
- 1497838 KB
- ·MCF5233
- FREESCALE [Freescale Semiconductor, Inc]
- Integrated Microprocessor Hardware Specification
- 1497838 KB
- ·MCF5234
- FREESCALE [Freescale Semiconductor, Inc]
- Integrated Microprocessor Hardware Specification
- 1497838 KB
- ·MCF5235
- FREESCALE [Freescale Semiconductor, Inc]
- Integrated Microprocessor Hardware Specification
- 1497838 KB
- ·MCF523X
- FREESCALE [Freescale Semiconductor, Inc]
- Integrated Microprocessor Hardware Specification
- 1497838 KB
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