MCM72CB32

Pinout




Specifications

Rating	Symbol	Value	Unit
Power Supply Voltage	VCC	0.5 to + 7.0	V
Voltage Relative to VSS for Any Pin Except VCC	Vin, Vout	0.5 to VCC + 0.5	V
Output Current (per I/O)	Iout	± 30	mA
Power Dissipation	PD	6.4	W
Temperature Under Bias	Tbias	10 to + 85	°C
Operating Temperature	TA	0 to +70	°C
Storage Temperature	Tstg	55 to + 125	°C

Description

The MCM72CB32SG and MCM72CB64SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor.

The modules are configured as 32K x 72 and 64K x 72 bits in a 160 pin card edge memory module. The module uses four of Motorola's MCM67C518 or MCM67C618 BiCMOS BurstRAMs.

Bursts of the MCM72CB32 can be initiated with either address status processor (ADSP ) or address status controller (ADSC ). Subsequent burst addresses are generated internal to the BurstRAM by the burst advance (ADV ) input pin.

Write cycles of the MCM72CB32 are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control.

The cache family is designed to interface with popular Pentium cache controllers with on board tag. PD0 PD2 are reserved for density and speed identification.