Purchase MG11, In-stock MG11 From SeekIC.
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MG11
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Suppliers
DataSheet
General Description
MG11 Maximum Ratings
Ambient temperature under bias (TA)
Military . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 55 to +125°C
Junction temperature . . . . . . . . . . . . . . . . . . TJ < TA + 20°C
Storage temperature . . . . . . . . . . . . . . . . . . 65 to +150°C
TTL/CMOS :
Supply voltage VDD . . . . . . . . . . . . . . . . . . . 0.5 V to +7 V
I/O voltage . . . . . . . . . . . . . . . .. . . . 0.5 V to VDD + 0.5 V
Stresses above those listed may cause permanent damage to the device. Explosure to absolute maximum rating conditions for extended period may affect device reliability.
Military . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 55 to +125°C
Junction temperature . . . . . . . . . . . . . . . . . . TJ < TA + 20°C
Storage temperature . . . . . . . . . . . . . . . . . . 65 to +150°C
TTL/CMOS :
Supply voltage VDD . . . . . . . . . . . . . . . . . . . 0.5 V to +7 V
I/O voltage . . . . . . . . . . . . . . . .. . . . 0.5 V to VDD + 0.5 V
Stresses above those listed may cause permanent damage to the device. Explosure to absolute maximum rating conditions for extended period may affect device reliability.
MG11 Features
Full Range of Matrices up to 500k Cells
0.6 m Drawn CMOS, 3 Metal Layers, Sea of Gates
RAM, DPRAM, FIFO Compilers
Library Optimised for Synthesis, Floor Plan & Automatic
Test Generation (ATG)
High Speed Performances :
250 ps Typical Gate Delay @5 V
350 MHz Toggle Frequency @5 V
High System Frequency Skew Control :
250 MHz PLL for Clock Generation
Clock Tree Synthesis Software
3 & 5 Volts Operation; Single or Dual Supply Modes
Low Power Consumption :
0.9 W/Gate/MHz @3 V
2.4 W/Gate/MHz @5 V
Integrated Power on Reset
Matrices With More than 500 Pads
Standard 3, 6, 12m, 24mA I/Os, parallelism up to 48mA
Versatile I/O Cell : Input, Output, I/O, Supply, Oscillator
CMOS/TTL/PCI Interface
ESD (2 kV) And Latch-up Protected I/O
0.6 m Drawn CMOS, 3 Metal Layers, Sea of Gates
RAM, DPRAM, FIFO Compilers
Library Optimised for Synthesis, Floor Plan & Automatic
Test Generation (ATG)
High Speed Performances :
250 ps Typical Gate Delay @5 V
350 MHz Toggle Frequency @5 V
High System Frequency Skew Control :
250 MHz PLL for Clock Generation
Clock Tree Synthesis Software
3 & 5 Volts Operation; Single or Dual Supply Modes
Low Power Consumption :
0.9 W/Gate/MHz @3 V
2.4 W/Gate/MHz @5 V
Integrated Power on Reset
Matrices With More than 500 Pads
Standard 3, 6, 12m, 24mA I/Os, parallelism up to 48mA
Versatile I/O Cell : Input, Output, I/O, Supply, Oscillator
CMOS/TTL/PCI Interface
ESD (2 kV) And Latch-up Protected I/O
MG113P
PDF/DataSheet Download
- Datasheet: MG113P
- File Size: 285575 KB
- Manufacturer: OKI [OKI electronic componets]
- Click here to Download
- ·MG1
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- TOSHIBA [Toshiba Semiconductor]
- TECHNICAL DATA
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- TOSHIBA [Toshiba Semiconductor]
- TECHNICAL DATA
- 589613 KB
- ·MG100G2JL1
- TOSHIBA [Toshiba Semiconductor]
- TECHNICAL DATA
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- ·MG100G2YK1
- ETC [ETC]
- TRANSISTOR MODULES
- 306881 KB
- ·MG100G2YL1
- ETC [ETC]
- TRANSISTOR MODULES
- 49152 KB
- ·MG100H2YL1
- ETC [ETC]
- TRANSISTOR MODULES
- 306881 KB
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