MH1156E

Features:

High Speed - 180 ps Gate Delay - 2 input NAND, FO=2 (nominal)
Up to 1.198 M Used Gates and 512 Pins with 3.3 V, 3 V and 2.5 V Libraries when tested to space quality grades
Up to 1.6M Used Gates and 596 Pins with 3.3 V, 3 V and 2.5 V Libraries when tested to mil quality grades
System Level Integration Technology Cores on request:
  ` MEMORY: SRAMs, TPRAMs and FIFOs; Gate Level or Embedded, with EDACS
I/O Interfaces:
  ` CMOS, LVTTL, LVDS - Output Currents up to 24 mA, 5V Tolerant and compliant I/O
  ` cold sparing buffers (2 microA max. leakage current @ 3.6V worst case mil temp.)
300 MHz PLL, 260 MHz LVDS and 800 MHz max toggle frequency @ 3.3 V
Deep Submicron CAD Flow
Latch up immune and 200+ Krads total dose capability
SEU free cell
QML Q and V certification pending


Specifications

Operating Ambient
Temperature                                                     -55°C to +125°C
Storage Temperature                                       -65°C to +150°C
Maximum Input Voltage:
    Inputs V_DD                                                   +0.5V
    5V tolerant V_DD5                                          +0.5V
Maximum Operating Voltage                            3.6V

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.


Description

The MH1RT Series Gate Array and Embedded Array families from TEMIC are fabricated on a radiation tolerant 0.35 CMOS process, with up to 4 levels of metal for interconnect. This family features arrays with up to 1.6 million routable gates and 596 pins. The high density and high pin count capabilities of the MH1RT family, coupled with the ability to embed cores, or memory on the same silicon, makes the MH1RT series of arrays an ideal choice for System Level Integration.

The MH1RT series is supported by an advance software environment based on industry standards linking proprietary and commercial tools. Verilog, DFT, Sysnopsys and Vital are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle.

The MH1RT series comes as a dual use of the MH1 series, adding:
through process changes, the 100 MeV latch up immunity and the 200Krads+ total dose capability as required by most of the space programs,
through cells relayout, an SEU immunity allowing to SEU harden only where it is actually necessary with respect to function requirements.

The MH1RT series comes as the TEMIC 7 th generation of ASIC series designed for radiation hardened applications in a 15 years time frame.It is also made available to any of the currently available quality grades: commercial, industrial, automotive, military and space.