Purchase MH16D72AKLB-75, In-stock MH16D72AKLB-75 From SeekIC.
Part Number: MH16D72AKLB-75
Description: The MH16D72AKLB is 16777216 - word x 72-bit Double Data Rate(DDR) Sy nchronous...
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MH16D72AKLB-75
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DataSheet
General Description
MH16D72AKLB-75 General Description
The MH16D72AKLB is 16777216 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 9 industry standard 16M x 8 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory module is suitable for main memory in computer systems and easy to interchange or add modules.
MH16D72AKLB-75 Maximum Ratings
| Symbol | Parameter | Condition | Ratings | Unit |
| Vdd | Supply Voltage | with respect to Vss | -0.5 ~ 3.7 | V |
| VddQ | Supply Voltage for Output | with respect to VssQ | -0.5 ~ 3.7 | V |
| VI | Input Voltage | with respect to Vss | -0.5 ~ Vdd+0.5 | V |
| VO | Output Voltage | with respect to VssQ | -0.5 ~ VddQ+0.5 | V |
| IO | Output Current | 50 | mA | |
| Pd | Power Dissipation | Ta=25C | 10 | W |
| Topr | Operating Temperature | 0 ~ 70 | C | |
| Tstg | Storage Temperature | -45 ~ 100 | C |
MH16D72AKLB-75 Features
- Utilizes industry standard 16M X 8 DDR Synchronous DRAMs in TSOP package , industry standard Registered Buffer in TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data
- Dif f erential clock inputs (CK0 and /CK0)
- data and data mask ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cycles /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-9
- SSTL_2 Interf ace
- Module 1bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data
- Dif f erential clock inputs (CK0 and /CK0)
- data and data mask ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cycles /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-9
- SSTL_2 Interf ace
- Module 1bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
MH16D72AKLB-75 Typical Application
Main memory unit for PC, PCserver
MH16D72AKLB-75
PDF/DataSheet Download
- Datasheet: MH16D72AKLB-75
- File Size: 356540 KB
- Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
- Click here to Download
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The MH16D72AKLB is 16777216 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.MH16D72AKLBconsists of 9 industry standard 16M x 8 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MH...
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