MH2RT

The Atmel MH2RT cell-based ASIC series are fabricated on a 0.25 micron CMOS process, with up to five levels of metal. This family allows up to 5 million gates and 800 pads. The high density and high pin count capabilities of the MH2RT family, coupled with the ability to embed processor cores or memories on the same silicon, make the MH2RT series an ideal choice for System Level Integration.

The MH2RT series is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Verilog^®, DFT, Synopsys^® and Vital are the reference front-end tools. The Cadence™ "Logic Design Planner" floor planning associated with timing driven layout provides an efficient back-end cycle.

The MH2RT series comes as a dual use of the MH2 series adding:
- through process changes, the 100 MeV latch up immunity and the 200 Krads+ total dose capability as required by most of the space programs,
- through cells layout, an SEU immunity allowing to SEU harden only where it is actually necessary with respect to function requirements.

The MH2RT series comes as the Atmel 8th generation of ASIC series designed for radiation hardened applications in 19 years.

It will be made available to any of the currently available quality grades, including QML Q and V.

The Atmel MH2RT family is fabricated on a proprietary 0.25 micron five-layer-metal CMOS process intended for use with a supply voltage of 2.5V ± 0.2V. The MH2RT Series is offered with a mutli-project wafer service.