Purchase MH32S72PHB -8, In-stock MH32S72PHB -8 From SeekIC.
Part Number: MH32S72PHB -8
Description: BANK ACTIVATEThe SDRAM has four independent banks. Each bank is activated by the ACT command with the bank address(...
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MH32S72PHB -8
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DataSheet
General Description
MH32S72PHB -8 General Description
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum activation interval between one bank and the other bank is tRRD.The number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates indicated by BA. When both banks are active, the precharge all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command can be issued.
MH32S72PHB -8 Maximum Ratings
| Symbol | Parameter | Condition | Ratings | Unit |
| Vdd | Supply Voltage | with respect to Vss | -0.5 ~ 4.6 | V |
| VI | Input Voltage | with respect to Vss | -0.5 ~ 4.6 | V |
| VO | Output Voltage | with respect to Vss | -0.5 ~ 4.6 | V |
| IO | Output Current | 50 | mA | |
| Pd | Power Dissipation | Ta=25°C | 16 | W |
| Topr | Operating Temperature | 0 ~ 70 | °C | |
| Tstg | Storage Temperature | -40 ~ 100 | °C |
MH32S72PHB -8 Features
·Utilizes industry standard 16M x 8 Synchronous DRAMs TSOP and industry standard EEPROM in TSSOP
·168-pin (84-pin dual in-line package)
·single 3.3V±0.3V power supply
·Clock frequency 100MHz
·Fully synchronous operation referenced to clock rising edge
·4 bank operation controlled by BA0,1(Bank Address)
·/CAS latency- 2/3(programmable)
·Burst length- 1/2/4/8/Full Page(programmable)
·Burst type- sequential / interleave(programmable)
·Column access - random
·Auto precharge / All bank precharge controlled by A10
·Auto refresh and Self refresh
·4096 refresh cycle /64ms
·LVTTL Interface
·Discrete IC and module design conform to PC100 specification.
(module Spec. Rev. 1.0 and SPD 1.2A(-7,-8), SPD 1.0(-10))
·168-pin (84-pin dual in-line package)
·single 3.3V±0.3V power supply
·Clock frequency 100MHz
·Fully synchronous operation referenced to clock rising edge
·4 bank operation controlled by BA0,1(Bank Address)
·/CAS latency- 2/3(programmable)
·Burst length- 1/2/4/8/Full Page(programmable)
·Burst type- sequential / interleave(programmable)
·Column access - random
·Auto precharge / All bank precharge controlled by A10
·Auto refresh and Self refresh
·4096 refresh cycle /64ms
·LVTTL Interface
·Discrete IC and module design conform to PC100 specification.
(module Spec. Rev. 1.0 and SPD 1.2A(-7,-8), SPD 1.0(-10))
MH32S72PHB -8 Typical Application
PC main memory
MH32S72PHB -8
PDF/DataSheet Download
- Datasheet: MH32S72PHB -8
- File Size: 609355 KB
- Manufacturer: Mitsubishi
- Click here to Download
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MH32S72PHB -8 Relative Products
MH32S72PHB -7
BANK ACTIVATEThe SDRAM MH32S72PHB -7has four independent banks. Each bank is activated by the ACT command with the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum activation interval between one bank and the other bank is tRRD.T...
MH32S72PHB -10
BANK ACTIVATEThe SDRAM MH32S72PHB -10has four independent banks. Each bank is activated by the ACT command with the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum activation interval between one bank and the other bank is tRRD....
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