Purchase MH64D64AKQH-75, In-stock MH64D64AKQH-75 From SeekIC.
Part Number: MH64D64AKQH-75
Description: The MH64D64AKQH is 67108864 - word x 64-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.This consist...
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MH64D64AKQH-75
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DataSheet
General Description
MH64D64AKQH-75 General Description
The MH64D64AKQH is 67108864 - word x 64-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 16 industry standard 32M x 8 DDR Sy nchronous DRAMs in Small TSOP with SSTL_2 interf ace which achieves v ery high speed data rate up to 133MHz.
This socket-ty pe memory module is suitable for main memory in computer systems and easy to interchange or add modules.
MH64D64AKQH-75 Maximum Ratings
|
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
|
Vdd |
Supply Voltage |
With respect to Vss |
-0.5 ~ 3.7 |
V |
|
VI |
Input Voltage |
With respect to Vss |
-0.5 ~ Vdd+0.5 |
V |
|
VO |
Output Voltage |
With respect to Vss |
-0.5 ~ Vdd+0.5 |
V |
|
IO |
Output Current |
50 |
mA | |
|
Pd |
Power Dissipation |
Ta=25°C |
13 |
W |
|
Topr |
Operating Temperature |
0~ 70 |
°C | |
|
Tstg |
Storage Temperature |
-45~ 100 |
°C |
MH64D64AKQH-75 Features
- Utilizes industry standard 32M X 8 DDR Synchronous DRAMs in Smal TSOP package , industry standard EEPROM(SPD) in TSSOP package
- 200pin SO-DIMM
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data
- Dif f erential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transition edges of DQS
- Commands entered on each positiv e CLK edge
- Data and data mask ref erenced to both edges of DQS
- 4bank operation concontrolled by BA0,BA1(Bank Address ,discrete)
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Ty pe - sequential/interleav e(programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 ref resh cycles /64ms
- Auto ref resh and Self ref resh
- Row address A0-12 / Column address A0-9
- SSTL_2 Interf ace
- Module 2bank Conf igration
- 200pin SO-DIMM
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data
- Dif f erential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transition edges of DQS
- Commands entered on each positiv e CLK edge
- Data and data mask ref erenced to both edges of DQS
- 4bank operation concontrolled by BA0,BA1(Bank Address ,discrete)
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Ty pe - sequential/interleav e(programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 ref resh cycles /64ms
- Auto ref resh and Self ref resh
- Row address A0-12 / Column address A0-9
- SSTL_2 Interf ace
- Module 2bank Conf igration
MH64D64AKQH-75 Typical Application
Main memory unit for Note PC, Mobile etc.
MH64D64AKQH-75
PDF/DataSheet Download
- Datasheet: MH64D64AKQH-75
- File Size: 371523 KB
- Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]
- Click here to Download
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The MH64D64AKQH is 67108864 - word x 64-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module.MH64D64AKQH consists of 16 industry standard 32M x 8 DDR Sy nchronous DRAMs in Small TSOP with SSTL_2 interf ace which achieves v ery high speed data rate up t...
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