MK5027

`CMOS
`FULLY COMPATIBLE WITH BOTH 8 OR 16 BIT SYSTEMS
`SYSTEM CLOCK RATE TO 10MHz. DATA RATE UP TO 2.5Mbps FOR SS7 PROTOCOL PROCESSING,7Mbps FOR TRANSPARENT HDLC MODE
`COMPLETE LEVEL 2 IMPLEMENTATION
`COMPATIBLE WITH 1988 CCITT, AT&T, ANSI, AND BELLCORE SIGNALLING SYSTEM NUMBER 7 LINK LEVEL PROTOCOLS
`52 PIN PLCC AND 48-PIN DIP PIN-FOR-PIN COMPATIBLE WITH THE SGS-THOMSON X.25 CHIP (MK5025) AND NEARLY PIN-FORPIN COMPATIBLE WITH THE SGS-THOMSON VLANCE CHIP (MK5032)
`BUFFER MANAGEMENT INCLUDES: - Initialization Block - Separate Receive and Transmit Rings - Variable Descriptor Ring and Window Sizes.
`ON CHIP DMA CONTROL WITH PROGRAMMABLE BURST LENGTH
`SELECTABLE BEC OR PCR RETRANSMISSION METHODS, INCLUDING FORCED RETRANSMISSIONFOR PCR
`HANDLES ALL 7 SS7 TIMERS
`HANDLES ALL SS7 FRAME FORMATTING: - Zero bit insert and delete - FCS generation and detection - Frame delimiting with flags
`PROGRAMMABLE MINIMUM SIGNAL UNIT
`SPACING(number of flags between SU's)
`HANDLES ALL SEQUENCING AND LINK CONTROL
`SELECTABLE FCS OF 16 OR 32 BITS.
`TESTING FACILITIES: - Internal Loopback - Silent Loopback - Optional Internal Data Clock Generation - Self Test
`ALL INPUTS AND OUTPUTS ARE TTL COMPATIBLE
`PROGRAMMABLE FOR FULL OR HALF DUPLEX OPERATION