MM74HC646

These transceivers MM74HC646 utilize advanced silicon-gate CMOS technology, and contain two sets of TRI-STATE. outputs, two sets of D-type flip-flops, and control circuitry designed for high speed multiplexed transmission of data. Six control inputs enable this device to be used as a latched transceiver, unlatched transceiver, or a combination of both. As a latched transceiver, data from one bus is stored for later retrieval by the other bus. Alternately real time bus data (unlatched) of MM74HC646 may be directly transferred from one bus to another.

Circuit operation of MM74HC646 is determined by the G, DIR, CAB, CBA, SAB, SBA control inputs. The enable input, G, controls whether any bus outputs are enabled. The direction control, DIR, determines which bus is enabled, and hence the direction data flows: The SAB, SBA inputs control whether the latched data (stored in D type flip flops), or the bus data (from other bus input pins) is transferred. Each set of flipflops has its own clock CAB, and CBA, for storing data. Data of MM74HC646  is latched on the rising edge of the clock.

Each output of MM74HC646 can drive up to 15 low power Schottky TTL loads. These devices are functionally and pin compatible to their LS-TTL counterparts. All inputs are protected from damage due to static discharge by diodes to VCC and ground.