MNDS3886A-X

Supply Voltage.................................................6.5V
Control Input Voltage.......................................6.5V
Driver Input and Receiver Output.....................5.5V
Receiver Input Current.................................+15mA
Bus Termination Voltage...................................2.4V
Power Dissipation at 25 C (CERPAC)
Derate at 11.5mW/ C above 25 C ...................1.7W
Storage Temperature Range..........-65 C to +150 C
Lead Temperature (Soldering, 4 seconds)......260 C
Note 1: "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: All input and/or output pins shall not exceed Vcc plus 0.5V and shall not exceed the absolute maximum rating at anytime, including power-up and power down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QVcc and Vcc. There is a diode between each input and/or output to Vcc which is forward biased when incorrect sequencing is applied. Alternatively, a current limiting resistor can be used when pulling-up the inputs to prevent damage. The current into any input/output pin shall be no greater than 50mA. Exception, LI and Bn pins do not have power sequencing requirements with respect to Vcc and QVcc. Furthermore, the difference between Vcc and QVcc should never be greater than 0.5V at any time including power-up.

The DS3886A is one in a series of transceivers designed specifically for the implementation of high performance Futurebus+ and proprietary bus interfaces. The DS3886A is a BTL 9-Bit Latching Data Transceiver designed to conform to IEEE 1194.1 (Backplane Transceiver Logic-BTL) as specified in the IEEE 896.2 Futurebus+ specification. The DS3886A incorporates an edge-triggered latch in the driver path which can be bypassed during fall-through mode of operation and a transparent latch in the receiver path. Utilization of the DS3886A simplifies the implementation of byte wide address/data with parity lines and also may be used for the Futurebus+ status, tag and command lines. The DS3886A driver output configuration is an NPN open collector which allows Wired-OR connection on the bus. Each driver output incorporates a Schottky diode in series with it's collector to isolate the transistor output capacitance from the bus, thus reducing the bus loading in the inactive state. The combined output capacitance of the driver output and receiver input is less than 5pF. The DS3886A driver also has high sink current capability to comply with the bus loading requirements defined within IEEE 1194.1 BTL specification.

Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semiconductor, then developed by the IEEE to enhance the performance of backplane buses. BTL compatible transceivers feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption and receivers with precision thresholds for maximum noise immunity. The BTL standard eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected to match the bus impedance) connected to 2.1V at both ends. The low voltage is typically 1V at 25/125 C and 1.1V at -55 C. Separate ground pins are provided for each BTL output to minimize induced ground noise during simultaneous switching. The unique DS3886A driver circuitry meets the maximum slew rate of 0.5 V/ns which allows controlled rise and fall times to reduce noise coupling to adjacent lines. The transceiver's high impedance control and driver inputs are fully TTL compatible. The receiver is a high speed comparator that utilizes a Bandgap reference for precision threshold control, allowing maximum noise immunity to the BTL 1V signaling level. Separate QVcc and QGND pins are provided to minimize the effects of high current switching noise. The output is TRI-STATE and fully TTL compatible.

The DS3886A supports live insertion as defined in IEEE 896.2 through the LI (Live Insertion) pin. To implement live insertion the LI pin should be connected to the live insertion power connector. If this function is not supported, the LI pin must be tied to the Vcc pin. The DS3886A also provides glitch free power up/down protection during power sequencing.

The DS3886A has two types of power connections in addition to the LI pin. They are the Logic Vcc (Vcc) and the Quiet Vcc (QVcc). There are two Logic Vcc pins on the DS3886A that provide the supply voltage for the logic and control circuitry. Multiple connections are provided to reduce the effects of package inductance and thereby minimize switching noise. As these pins are common to the Vcc bus internal to the device, a voltage delta should never exist between these pins and the voltage difference between Vcc and QVcc should never exceed +0.5V because of ESD circuitry.

When CD (Chip Disable) is high, An is in high impedance state and Bn is high. To transmit data (An to Bn) the T/R signal is high.When RBYP is high, the positive edge triggered flip-flop is in the transparent mode. When RBYP is low, the positive edge of the ACLK signal clocks the data. In addition, the DS3886A ESD circuitry between the Vcc pins and all other pins except for BTL I/O's and LI pins requires that any voltage on these pins should not exceed the voltage on Vcc +0.5V.

There are three different types of ground pins on the DS3886A; the logic ground (GND), BTL grounds (B0GND-B8GND) and the Bandgap reference ground (QGND). All of these ground reference pins are isolated within the chip to minimize the effects of high current switching transients. For optimum performance the QGND should be returned to the connector through a quiet channel that does not carry transient switching current. The GND and B0GND-B8GND should be connected to the nearest backplane ground pin with the shortest possible path.

Since many different grounding schemes of DS3886A could be implemented and ESD circuitry exists on the DS3886A, it is important to note that any voltage difference between ground pins, QGND, GND or B0GND-B8GND should not exceed +0.5V including power up/down sequencing. Additional transceivers included in the Futurebus+ family are; the DS3884A BTL Handshake Transceiver featuring selectable Wired-OR glitch filtering, the DS3885 BTL Arbitration Transceiver with arbitration competition logic for the AB<7:0>/ABP signal lines.The DS3875 Arbitration Controller included in the Futurebus+ family supports all the required and optional modes for Futurebus+ arbitration protocol. It is designed to be used in conjunction with the DS3884A and DS3885 transceivers. All of the transceivers are offered in 48-pin CERPAC package.