MP7543

V_DD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Digital Input Voltage to GND (2) . . .GND 0.5 to V_DD +0.5 V
IOUT1, IOUT2 to GND . . . . . . . . . . .GND 0.5 to V_DD +0.5 V
VREF to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
VRFB to GND (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  .+25 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V
(Functionality Guaranteed +0.5 V)
Storage Temperature . . . . . . . . . . . . . .65°C to +150°C
Lead Temperature (Soldering, 10 seconds) . . . . . .+300°C
Package Power Dissipation Rating to 75°C
CDIP, PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . .700mW
Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 10mW/°C
NOTES:
1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms.
3 GND refers to AGND and DGND.

The MP7543 is a precision, 12-bit CMOS 4-quadrant multiplying Digital-to-Analog Converter designed for serial interface applications.

The MP7543 consists of two 12-bit registers, control logic and a 12-bit multiplying D/A converter. The input register (register A) is a 12-bit serial-in parallel-out shift register. Serial data at the SR1 pin is clocked into Register A on the leading or trailing edge (user selected) of the strobe input, with the MSB loaded first. Register B is a 12-bit parallel-in parallel-out register that follows register A. The contents of register A are loaded into register B under control of the Load inputs.

A CLEAR input is provided for the asynchronous resetting of register B to all 0's.

The MP7543 is manufactured using an advanced thin film monolithic CMOS fabrication process. A unique decoding technique is utilized yielding excellent accuracy and stability. 12-bit linearity is achieved without laser trimming.

The MP7543 reduces the additional linearity errors due to output amplifier offset to only 330 mV per millivolt of offset - half the value of a standard R-2R CMOS DAC design approach.