Purchase MPC2002, In-stock MPC2002 From SeekIC, PDF Datasheet Download.

Part Number:
MPC2002
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Description：
The MPC2002SG and MPC2003SG are designed to provide a burstable, high performance, 2

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General Description

The MPC2002SG and MPC2003SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the PowerPC 60x processors. The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses four of Motorola’s MCM67M518 or MCM67M618 BiCMOS BurstRAMs.

Bursts can be initiated with either transfer start processor (TSP) or transfer start controller (TSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst address advance (BAA) pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control.

The cache family is designed to interface with the PowerPC 60x bus and requires external tag. PD0 – PD2 are reserved for density and speed identification.

Maximum Ratings

Rating	Symbol	Value	Unit
Power Supply Voltage	V_CC	– 0.5 to + 7.0	V
Voltage Relative to VSS for Any Pin Except VCC	V_in,V_out	– 0.5 to VCC + 0.5	V
Output Current (per I/O)	I_out	± 30	mA
Power Dissipation	P_D	± 30	W
Temperature Under Bias	T_bias	– 10 to + 85	℃
Operating Temperature	T_A	0 to +70	℃
Storage Temperature	T_stg	– 55 to + 125	℃

Features

• PowerPC–style Burst Counter on Board
• Dual Readout SIMM for Circuit Density
• Single 5 V ± 5% Power Supply
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Byte Parity
• Byte Write Capability
• Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz
• Decoupling Capacitors for each Fast Static RAM
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
• I/Os are 3.3 V Compatible