MPC801 Selling Leads, Price trend, MPC801 DataSheet download, circuit diagram from SeekIC.com

Features: The following is a list of the main features of the MPC801:• Embedded PowerPC core with 52 MIPS at 40 MHz (using Dhrystone 2.1)• Single-issue, 32-bit version of the embedded PowerPC core (fully compatible with the PowerPC User Instruction Set Architecture (Book I)) with 32* 3...

See larger image

SeekIC No. : 004426082 Detail

MPC801: Features: The following is a list of the main features of the MPC801:• Embedded PowerPC core with 52 MIPS at 40 MHz (using Dhrystone 2.1)• Single-issue, 32-bit version of the embedded Po...

MPC801 Data Sheet

Get Latest Price

Part Number:: MPC801
Supply Ability:: 5000

Price Break

Qty
1~5000

Unit Price
Negotiable

Processing time
15 Days

SeekIC Buyer Protection PLUS - newly updated for 2013!

Escrow Protection.
Guaranteed refunds.
Secure payments.
Learn more >>

Month Sales

268 Transactions

Rating

evaluate (4.8 stars)

Upload time: 2024/4/26

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.

Product Details

Description

Features:

The following is a list of the main features of the MPC801:
• Embedded PowerPC core with 52 MIPS at 40 MHz (using Dhrystone 2.1)
• Single-issue, 32-bit version of the embedded PowerPC core (fully compatible with the PowerPC User Instruction Set Architecture (Book I)) with 32* 32-bit fixed-point registers
-Embedded PowerPC core performs branch folding and branch prediction with conditional pre-fetch, but without conditional execution
-1K data cache and 2K instruction cache
-Instruction and data caches are two way, set-associative, physical address, 4 word line burst, least recently used (LRU) replacement, lockable online granularity
-MMUs with 8-entry TLB, fully associative instruction and data TLBs
-MMUs support 4K, 16K, 512K and 8M page sizes; 16 virtual address spaces and 16 protection groups
-Advanced on-chip emulation debug mode
• Up to 32-bit data bus (dynamic bus sizing for 8,16, and 32 bits controlled by memory controller)
• 26 external address lines
• Complete static design (040 MHz operation)
• Memory controller (eight banks)
-Contains complete dynamic random-access memory (DRAM) controller
-Each bank can be a chip-select or RAS to support a DRAM bank
-Up to 30 wait states programmable per memory bank
-Glueless interface to DRAM single in-line memory modules (SIMMs), static random-access memory (SRAM), electrically programmable read-only memory (EPROM), and FLASH EPROM.
-DRAM controller programmable to support a wide range of sizes and speed DRAM memory.
-Four CAS lines, four WE lines, and one OE line
-Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
-Variable block sizes (32K to 256M)
-Selectable write protection
• System integration unit
-Bus monitor
-Software watchdog
-Periodic interrupt timer
-Low-power stop mode
-Clock synthesizer
-On-chip bus arbitration logic
-PowerPC decrementer
-PowerPC timebase
-RTC
-Reset controller
-IEEE 1149.1 test access port (JTAG)
• Interrupts
-Eight external interrupt request (IRQ0-7) lines
-Internal interrupt sources: SPI, I2C, UART1, UART2, TB, PIT, and RTC
• UART support
-Two UARTs
-Standard baud rates of 300 bps to 115.2 kbps with 16 * sample clock
-External 1 *clock for high-speed synchronous communication
-Flexible 5-wire serial interface
-Direct support of IrDA physical layer protocol
-8-byte FIFOs for transmit and receive
-Programmable data format
-Seven or eight data bits plus parity
-Odd, even, no parity, or force parity error
-One or two stop bits
-Programmable channel modes (normal and local loopback)
-Parity, framing, and overrun error detection
-Generation and detection of break
-Robust receiver data sampling with noise filtering
-Eight maskable interrupts
-Low-power idle mode
• I²C support
-Two-wire interface (SDA and SCL)
-Full-duplex operation
-Master or slave I2C mode support
-Multi-master environment support
-Clock rate support at a maximum of 520 KHz (assuming a 25-MHz system clock)
-Local loopback capability for testing
• SPI support
-Four-wire interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL)
-Full-duplex operation
-8- and 1-bit data character operation
-Back-to-back character transmission and reception support
-Master or slave SPI modes support
-Multi-master environment support
-Clock rates support at a maximum of 6.25 MHz in master mode and 12.5 MHz in slave mode (assuming a 25-MHz system clock)
-Independent programmable baud rate generator
-Programmable clock phase and polarity
-Open-drain output pins support multi-master configuration
-Local loopback capability for testing
• Low-power support
-Full onall units fully powered
-Dozecore functional units disabled except timebase decrementer, PLL, memory controller, and RTC in low-power standby
-Sleepall units disabled except RTC and PIT (PLL active for fast wake-up)
-Deep sleepall units disabled (including PLL), except RTC and PIT
• Debug interface
-Eight comparators (four operate on instruction address, two operate on data address, and two operate on data)
-Supports =< > conditions
-Each watchpoint can generate a breakpoint internally
• 3.3 V operation with 5-V TTL compatibility
• 256-pin ball grid array (BGA) package
The MPC801 is a combination of the embedded PowerPC core and integrated peripherals brought together to
meet the demands of various communications and networking products. The MPC801 is comprised of six
modules that all use the 32-bit internal bus:
• Embedded PowerPC core
• System integration unit
• Two UARTs
• I²C
• SPI
The MPC801 block diagram is illustrated in Figure 1 below.

Application

The MPC801 device is specifically designed to be a general-purpose, low-cost entry point to the embedded PowerPC Family at Motorola. The device excels in applications that require the performance of a single-issue PowerPC core with moderate amounts of data and instruction cache. It can support alternate bus masters in addition to providing all the basic features of glueless memory connections, but does not provide a wealth of serial connectivity. Instead, it supplies simple UART serial channels as well as I²C and SPI channels for onboard communication to other peripheral chips.

The MPC801 excels in low-power and portable applications due to its expansive power-down modes. In addition, the normal operation current is low. The MPC801 is ideal for applications where a significant portion of the user's added value is in peripherals or ASICs and a low-cost general-purpose CPU is required. The programmable flexibility of the memory controller ensures that the board design can accommodate future memory types without hardware changes, thus enabling the ASIC to concentrate on other system goals

MPC801

product image

floor Price/Ceiling Price

Price Break

Month Sales

Rating

Payment Methods

Recent History

Description

Customers Who Bought This Item Also Bought

Integrated Circuits (ICs)(111140)

Boxes, Enclosures, Racks(2218)

Computers, Office - Components, Accessories(4539)

Motors, Solenoids, Driver Boards/Modules(2035)

Transformers(1503)

Capacitors(4587)