MPC953

The MPC953 is a 3.3V compatible, PLL based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 110MHz and output skews of 150ps the MPC953 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycletocycle and phase jitter.
• Fully Integrated PLL
• Output Frequency up to 110MHz in PLL Mode
• Outputs Disable in High Impedance
• LQFP Packaging
• 100ps CycletoCycle Jitter
The MPC953 has a differential LVPECL reference input along with an external feedback input. These features make the MPC953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and tristate the output buffers when driven "high".

The MPC953 is fully 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the ability to drive terminated 50W transmission lines. For series terminated 50W lines, each of the MPC953 outputs can drive two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7mm 32lead LQFP package to provide the optimum combination of board density and performance.