MPC9992

The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback frequency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input reference frequency range.

The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC generator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between output frequencies.

The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.

The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted. Assertion of the reset signal forces all outputs to the logic low state.

The MPC9992 is fully 3.3V compatible and requires no external loop filter components. The differential clock input (PCLK) is PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels with the capability to drive terminated 50 transmission lines.

The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package. 1. Final specification of this parameter is pending characterization.