MT28C128564W18

The MT28C128532W18/W30D and MT28C128564W18/W30D combination Flash and CellularRAM are high-performance, high-density, memory solutions that can significantly improve system performance. The Flash architecture features a multipartition configuration that supports READ-while-PROGRAM/ERASE operations with no latency. A 4Mb partition size enables optimal design flexibility.Two Flash devices are stacked to achieve the 128Mb density. Each Flash die has a dedicated CE# and OE# control, enabling each Flash to be independently selectable.The MT28C128532W18/W30D and MT28C128564W18/W30D stacked Flash devices enable soft protection for blocks, as read only, by configuring soft protection registers with dedicated command sequences. For security purposes, two userprogrammable 64-bit chip protection registers are provided for each Flash device.

The embedded WORD PROGRAM and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). An on-chip device status register can be used to monitor the WSM status and determine the progress of the PROGRAM/ERASE tasks.

Each Flash device has a read configuration register (RCR) that defines how the Flash interacts with the memory bus. For device specifications and additional documentation concerning Flash and CellularRAM features,please refer to the MT28F644W18/W30 data sheet at www.micron.com/flash and the MT45W2MW16PFA and MT45W4MW16PFA data sheets at http://www.micron.com/cellularram.The CellularRAM architecture features high-speed CMOS, dynamic random-access memories developed for low-power portable applications The CellularRAM device is available in either 32Mb or 64Mb densities.

To operate seamlessly on a burst Flash bus, Cellular-RAM products have incorporated a transparent selfrefresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance.

The refresh configuration register (CR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and can be updated any time during normal operation. Special attention has been focused on standby current consumption during self-refresh.CellularRAM products include three system-accessible mechanisms used to minimize standby current.

Partial array refresh (PAR) limits refresh to the portion of the memory array being used. Temperature compensated refresh (TCR) is used to adjust the refresh rate according to the ambient temperature. The refresh rate can be decreased at lower temperatures to minimize current consumption during standby. Deep power down (DPD) halts the REFRESH operation altogether and is used when no vital information is stored in the device. These three refresh mechanisms are adjusted through the CR.

Please refer to Micron's Web site www.micron.com/flash for the latest MT28F644W18/W30 Flash data sheet and http://www.micron.com/cellularram for the latest MT45W2MW16PFA and MT45W4MW16PFA CellularRAM data sheet.