MT28C6428P20

The MT28C6428P20 and MT28C6428P18 combination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium. The dual-bank Flash devices are high-performance, high-density, nonvolatile memory with a revolutionary architecture that can significantly improve system performance.

This new architecture features:

• A two-memory-bank configuration supporting
   dual-bank operation;

• A high-performance bus interface providing a fast
   page data transfer; and

• A conventional asynchronous bus interface.

The devices also provide soft protection for blocks by configuring soft protection registers with dedicated command sequences. For security purposes, dual 64- bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). The WSM simplifies these operations and relieves the system processor of secondary tasks. An on-chip status register, one for each bank, can be used to monitor the WSM status to determine the progress of a PROGRAM/ERASE command.

The erase/program suspend functionality allows compatibility with existing EEPROM emulation software packages.

The devices take advantage of a dedicated power source for the Flash memory (F_V_CC) and a dedicated power source for the SRAM (S_V_CC), both at 1.70V2.20V for optimized power consumption and improved noise immunity. A dedicated I/O power supply (V_CCQ) is provided with an extended range (1.70V2.20V), to allow a direct interface to most common logic controllers and to ensure improved noise immunity. The separate S_V_CC pin for the SRAM provides data retention capability when required. The data retention S_V_CC is specified as low as 1.0V. The MT28C6428P20 and MT28C6428P18 devices support two F_V_PP voltage ranges, an in-circuit voltage of 0.9V2.2V and a production compatibility voltage of 12V ±5%. The 12V ±5% F_V_PP2 is supported for a maximum of 100 cycles and 10 cumulative hours.

The MT28C6428P20 and MT28C6428P18 contain an asynchronous 8Mb SRAM organized as 512K-words by 16 bits. The devices are fabricated using an advanced CMOS process and high-speed/ultra-lowpower circuit technology, and then are packaged in a67-ball FBGA package with 0.80mm pitch.