Purchase MT28F642D20, In-stock MT28F642D20 From SeekIC.
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MT28F642D20
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Suppliers
DataSheet
General Description
MT28F642D20 Maximum Ratings
Voltage to Any Ball Except VCC and VPP
with Respect to VSS ...............................-0.5V to +2.45V
VPP Voltage (for BLOCK ERASE and PROGRAM
with Respect to VSS) ............................-0.5V to +13.5V**
VCC and VCCQ Supply Voltage
with Respect to VSS ................................-0.3V to +2.45V
Output Short Circuit Current .................................100mA
Operating Temperature Range ..................-40 to +85
Storage Temperature Range ...................-55 to +125
Soldering Cycle ...........................................260 for 10s
with Respect to VSS ...............................-0.5V to +2.45V
VPP Voltage (for BLOCK ERASE and PROGRAM
with Respect to VSS) ............................-0.5V to +13.5V**
VCC and VCCQ Supply Voltage
with Respect to VSS ................................-0.3V to +2.45V
Output Short Circuit Current .................................100mA
Operating Temperature Range ..................-40 to +85
Storage Temperature Range ...................-55 to +125
Soldering Cycle ...........................................260 for 10s
MT28F642D20 Features
PIN ASSIGNMENT
59-Ball FBGA
• Single device supports asynchronous, page, and
burst operations
• Flexible dual-bank architecture
Support for true concurrent operation with zero
latency
Read bank a during program bank b and vice
versa
Read bank a during erase bank b and vice versa
• Basic configuration:
One hundred and thirty-five erasable blocks
Bank a (16Mb for data storage)
Bank b (48Mb for program storage)
• VCC, VCCQ, VPP voltages
1.70V (MIN), 1.90V (MAX) VCC, VCCQ
(MT28F642D18 only)
1.80V (MIN), 2.20V (MAX) VCC, and
2.25V (MAX) VCCQ (MT28F642D20 only)
1.80V (TYP) VPP (in-system PROGRAM/ERASE)
12V ±5% (HV) VPP tolerant (factory programming
compatibility)
• Random access time: 70ns @ 1.80V VCC1
• Burst Mode read access
MAX clock rate: 54 MHz (tCLK = 18.5ns)
Burst latency: 70ns @ 1.80V VCC and 54 MHz
tACLK: 15ns @ 1.80V VCC and 54 MHz
• Page Mode read access1
Four-/eight-word page
Interpage read access: 70ns @ 1.80V
Intrapage read access: 30ns @ 1.80V
• Low power consumption (VCC = 2.20V)
Asynchronous Read < 15mA
Interpage Read < 15mA
Intrapage Read < 5mA
Continuous Burst Read < 10mA
WRITE < 55mA (MAX)
ERASE < 45mA (MAX)
Standby < 50µA (MAX)
Automatic power save (APS) feature
Deep power-down < 25µA (MAX)
• Enhanced write and erase suspend options
• Accelerated programming algorithm (APA) insystem
and in-factory
• Dual 64-bit chip protection registers for security
purposes
NOTE: See page 7 for Ball Description Table.
See page 50 for mechanical drawing.
• Cross-compatible command support
Extended command set
Common flash interface
• PROGRAM/ERASE cycle
100,000 WRITE/ERASE cycles per block
OPTIONS MARKING
59-Ball FBGA
• Single device supports asynchronous, page, and
burst operations
• Flexible dual-bank architecture
Support for true concurrent operation with zero
latency
Read bank a during program bank b and vice
versa
Read bank a during erase bank b and vice versa
• Basic configuration:
One hundred and thirty-five erasable blocks
Bank a (16Mb for data storage)
Bank b (48Mb for program storage)
• VCC, VCCQ, VPP voltages
1.70V (MIN), 1.90V (MAX) VCC, VCCQ
(MT28F642D18 only)
1.80V (MIN), 2.20V (MAX) VCC, and
2.25V (MAX) VCCQ (MT28F642D20 only)
1.80V (TYP) VPP (in-system PROGRAM/ERASE)
12V ±5% (HV) VPP tolerant (factory programming
compatibility)
• Random access time: 70ns @ 1.80V VCC1
• Burst Mode read access
MAX clock rate: 54 MHz (tCLK = 18.5ns)
Burst latency: 70ns @ 1.80V VCC and 54 MHz
tACLK: 15ns @ 1.80V VCC and 54 MHz
• Page Mode read access1
Four-/eight-word page
Interpage read access: 70ns @ 1.80V
Intrapage read access: 30ns @ 1.80V
• Low power consumption (VCC = 2.20V)
Asynchronous Read < 15mA
Interpage Read < 15mA
Intrapage Read < 5mA
Continuous Burst Read < 10mA
WRITE < 55mA (MAX)
ERASE < 45mA (MAX)
Standby < 50µA (MAX)
Automatic power save (APS) feature
Deep power-down < 25µA (MAX)
• Enhanced write and erase suspend options
• Accelerated programming algorithm (APA) insystem
and in-factory
• Dual 64-bit chip protection registers for security
purposes
NOTE: See page 7 for Ball Description Table.
See page 50 for mechanical drawing.
• Cross-compatible command support
Extended command set
Common flash interface
• PROGRAM/ERASE cycle
100,000 WRITE/ERASE cycles per block
OPTIONS MARKING
MT28F642D20
PDF/DataSheet Download
- Datasheet: MT28F642D20
- File Size: 607276 KB
- Manufacturer: MICRON [Micron Technology]
- Click here to Download
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