MT46H16M16LF 4 Features
• VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• Four internal banks for concurrent operation
• Data masks (DM) for masking write dataone mask per byte
• Programmable burst lengths: 2, 4, 8, 16 or full page
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS compatible inputs
• On-chip temperature sensor to control refresh rate
• Partial array self refresh (PASR)
• Deep power-down (DPD)
• Selectable output drive (DS)
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