MT58L64L32D

Features: • Fast clock and OE# access times• Single +3.3V +0.3V/-0.165V power supply (VDD)• Separate +3.3V isolated output buffer supply (VDDQ)• SNOOZE MODE for reduced-power standby• Common data inputs and data outputs• Individual BYTE WRITE control and GLOBAL ...

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SeekIC No. : 004429971 Detail

MT58L64L32D: Features: • Fast clock and OE# access times• Single +3.3V +0.3V/-0.165V power supply (VDD)• Separate +3.3V isolated output buffer supply (VDDQ)• SNOOZE MODE for reduced-power...

floor Price/Ceiling Price

Part Number:
MT58L64L32D
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/28

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Product Details

Description



Features:

• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (VDD)
• Separate +3.3V isolated output buffer supply (VDDQ)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and address pipelining
• Clock-controlled and registered addresses, data I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 options available



Pinout

  Connection Diagram


Specifications

Voltage on VDD Supply
    Relative to Vss .................................... -0.5V to +4.6V
Voltage on VDDQ Supply
    Relative to Vss .................................... -0.5V to +4.6V
VIN  ............................................... -0.5V to VDDQ + 0.5V
Storage Temperature (plastic) ............ -55°C to +150°C
Junction Temperature** .................................... +150°C
Short Circuit Output Current     ........................... 100mA



Description

The Micron® SyncBurst™ SRAM family MT58L64L32D employs high- speed, low-power CMOS designs that are fabri-cated using an advanced CMOS process.

Micron's 2Mb SyncBurst SRAMs MT58L64L32D integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registerscontrolled by a positive-edge-triggered single clock input (CLK). The synchronous inputs of MT58L64L32D include all ad-
dresses, all data inputs, active LOW chip enable (CE#),two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) and global write (GW#).

Asynchronous inputs of MT58L64L32D include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode pin (MODE) that selects between inter- leaved and linear burst modes. The data-out (Q), en-abled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs.

Burst operation of MT58L64L32D can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#).

Address and write control of MT58L64L32D are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls




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