MFG:Other Category:Other
Category: Other
MFG: Other
Description: The MT9041BP is one member of the MT9041 family which is designed as the T1/E1 system synchronizer device that can be use...
The MT9041BP is one member of the MT9041 family which is designed as the T1/E1 system synchronizer device that can be used in (1)Synchronization and timing control for multitrunk T1 and E1 systems; (2)ST-BUS clock and frame pulse sources applications. This MT9041BP generates ST-BUS clock and framing signals, and will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, capture range and phase change slope requirements for these specifications.
Features of the MT9041BP are:(1)Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 4 Enhanced and Stratum 4 timing for DS1 Interfaces; (2)Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 Interfaces; (3)Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals; (4)Provides C1.5, C2, C3, C4, C8 and C16 output clock signals; (5)Provides 3 different styles of 8 KHz framing pulses; (6)Attenuates wander from 1.9 Hz.
The absolute maximum ratings of the MT9041BP can be summarized as:(1)Supply voltage: -0.3 to 7.0 V;(2)Voltage on any pin: -0.3 to VDD+0.3 V;(3)Current on any pin: 20 mA;(4)Storage temperature: -55 to 125 °C;(5)PLCC package power dissipation: 900 mW. If you want to know more information about MT9041BP, please download the datasheet in www.seekic.com or www.chinaicmart.com .
MT9041BP
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The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are p...
The MT9041AP is one member of the MT9041 family which is designed as the T1/E1 system synchronizer device that can be used in (1)Synchronization and timing control for multitrunk T1 and E1 systems; (2)ST-BUS clock and frame pulse sources applications. This d...
The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized ...
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