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Part Number: MT9075B
Description: The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface U...
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MT9075B
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DataSheet
General Description
MT9075B General Description
The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU).
The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU interfaces the framer functions to the PCM 30 transformer-isolated four wire line.
The MT9075B meets or supports the latest ITU-T Recommendations including G.703, G.704, G.706, G.732, G.775, G.796, G.823 for PCM 30, and I.431 for ISDN primary rate. It also meets or supports ETSI ETS 300 011, ETS 300 166 and ETS 300 233 as well as BS 6450.
MT9075B Maximum Ratings
| Parameter | Symbol | Min | Max | Units | |
| 1 | Supply Voltage | VDD | - 0.3 | 7 | V |
| 2 | Voltage at Digital Inputs | VI | - 0.3 | VDD + 0.3 | V |
| 3 | Current at Digital Inputs | II | 30 | mA | |
| 4 | Voltage at Digital Outputs | VO | - 0.3 | VDD + 0.3 | V |
| 5 | Voltage at Digital Outputs | IO | 30 | mW | |
| 6 | Storage Temperature | TST | -55 | 125 |
MT9075B Features
• Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package
• Selectable bit rate data link access with optional Sa bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1)
• LIU dynamic range of 20 dB
• Enhanced performance monitoring and programmable error insertion functions
• Low jitter DPLL for clock generation
• Operating under synchronized or free run mode
• Two-frame receive elastic buffer with controlled slip direction indication
• Selectable transmit or receive jitter attenuator
• Intel or Motorola non-multiplexed parallel microprocessor interface
• CRC-4 updating algorithm for intermediate path points of a message-based data link application
• ST-BUS/GCI 2.048 Mbit/s backplane bus for both data and signalling
• Selectable bit rate data link access with optional Sa bits HDLC controller (HDLC0) and channel 16 HDLC controller (HDLC1)
• LIU dynamic range of 20 dB
• Enhanced performance monitoring and programmable error insertion functions
• Low jitter DPLL for clock generation
• Operating under synchronized or free run mode
• Two-frame receive elastic buffer with controlled slip direction indication
• Selectable transmit or receive jitter attenuator
• Intel or Motorola non-multiplexed parallel microprocessor interface
• CRC-4 updating algorithm for intermediate path points of a message-based data link application
• ST-BUS/GCI 2.048 Mbit/s backplane bus for both data and signalling
MT9075B Typical Application
• E1 add/drop multiplexers and channel banks
• CO and PBX equipment interfaces
• Primary Rate ISDN nodes
• Digital Cross-connect Systems (DCS)
• CO and PBX equipment interfaces
• Primary Rate ISDN nodes
• Digital Cross-connect Systems (DCS)
MT9075B Connection Diagram
MT9075B
PDF/DataSheet Download
- Datasheet: MT9075B
- File Size: 355358 KB
- Manufacturer: MITEL [Mitel Networks Corporation]
- Click here to Download
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