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MFG:MT Package Cooled:QFP
Part Number: MT90826
MFG: MT
Package Cooled: QFP
Description: The MT90826 Quad Digital Switch has a nonblocking switch capacity of 4,096 x 4,096 channels at a seria...
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MT90826
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DataSheet
General Description
MT90826 General Description
The MT90826 Quad Digital Switch has a nonblocking switch capacity of 4,096 x 4,096 channels at a serial bit rate of 8.192Mb/s or 16.384 Mb/s, 2,048 x 2,048 channels at 4.096Mb/s and 1024 x 1024 channels at 2.048Mb/s. The device has many features that are programmable on a per stream or per channel basis, including message mode, input offset delay and high impedance output control.
The per stream input and output delay control is particularly useful for managing large multi-chip switches with a distributed backplane.
Operating in Split Rate mode allows for switching between two groups of bit rate streams.
MT90826 Maximum Ratings
| Parameter | Symbol | Min | Max | Units | |
| 1 | Supply Voltage | VDD | -0.3 | 5.0 | V |
| 2 | Voltage on any 3.3V tolerant pin I/O (other than supply pins) |
VI | VSS - 0.3 | VDD + 0.3 | V |
| 3 | Voltage on any 5V tolerant pin I/O (other than supply pins) |
VI | VSS - 0.3 | 5.0 | V |
| 4 | Continuous Current at digital outputs | Io | 20 | mA | |
| 5 | Package power dissipation | PD | 1 | W | |
| 6 | Storage temperature | TS | - 65 | +125 |
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied
MT90826 Features
• 4,096× 4,096 channel non-blocking switching at 8.192 or 16.384 Mb/s
• Per-channel variable or constant throughput delay
• Accept ST-BUS streams of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or 16.384 Mb/s
• Split Rate mode allows mix of two bit rates and rate conversions
• Automatic frame offset delay measurement for ST-BUS input and output streams
• Per-stream frame delay offset programming
• Per-channel high impedance output control
• Bit Error Monitoring on selected ST-BUS input and output channels.
• Per-channel message mode
• Connection memory block programming
• IEEE-1149.1 (JTAG) Test Port
• 3.3V local I/O with 5V tolerant inputs and TTL compatible outputs
• Per-channel variable or constant throughput delay
• Accept ST-BUS streams of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or 16.384 Mb/s
• Split Rate mode allows mix of two bit rates and rate conversions
• Automatic frame offset delay measurement for ST-BUS input and output streams
• Per-stream frame delay offset programming
• Per-channel high impedance output control
• Bit Error Monitoring on selected ST-BUS input and output channels.
• Per-channel message mode
• Connection memory block programming
• IEEE-1149.1 (JTAG) Test Port
• 3.3V local I/O with 5V tolerant inputs and TTL compatible outputs
MT90826 Typical Application
• Medium and large switching platforms
• CTI application
• Voice/data multiplexer
• Digital cross connects
• WAN access system
• Wireless base stations
• CTI application
• Voice/data multiplexer
• Digital cross connects
• WAN access system
• Wireless base stations
MT90826 Connection Diagram
MT90826
PDF/DataSheet Download
- Datasheet: MT90826
- File Size: 135713 KB
- Manufacturer: MITEL [Mitel Networks Corporation]
- Click here to Download
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