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Part Number: MU9C4K64-12

 

 

 

 

Description: The MU9C RCP family consists of 4K and 8K x 64-bit Routing Coprocessors (RCPs) with a 32-bit wide data...


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MU9C4K64-12 General Description


The MU9C RCP family consists of 4K and 8K x 64-bit Routing Coprocessors (RCPs) with a 32-bit wide data interface. The device is designed for use in layer 2 switches to provide very high throughput address translation using tables held in external RAM. The MU9C RCP has a fully deterministic search time, independent of the size of the list and the position of the data in the list. This unique feature guarantees that the wire speed address recognition does not impact the latency or induce some jitter on the latency of the global system. Address fields from the packet header are compared against a list of entries stored in the array. As a result of the comparison, the MU9C RCP generates an index that is used to access an external RAM where port mapping data and other associated information is stored.

A set of control states provides a powerful and flexible control interface to the MU9C RCP. This control structure allows memory read and write, register read and write, data move, comparison, validity control, addressing control, and initialization operations.

The MU9C RCP architecture uses direct hardware control of the device and an independent bus for returning match results. Software control is also supported for systems where maximum performance is not needed.

MU9C4K64-12 Maximum Ratings

Supply Voltage.............................................................................0.5 to 4.6 Volts
Voltage on all other pins..................................................-0.5 to VDD +0.5 Volts
                                                 (-2 Volts for 10 ns, measured at the 50% point)
Temperature under bias...........................................................-40` C to +85
Storage Temperature.............................................................-55` C to +125
DC Output Current......20 mA (per output, one at a time, one second duration)

MU9C4K64-12 Features

·  4K and 8K x 64-bit words  
·  64-bit binary compares  
·  35 ns deterministic compare and output time  
·  32-bit Data I/O port  
·  16-bit Match Address Output port  
·  Address/Control bus directly controls device operations for faster operation or higher throughput  
·  Seven selectable mask registers
·  Synchronous operation  
·  Cascadable for increased depth
·  Extensive set of control states for flexibility
·  JTAG interface
·  100-pin LQFP package; 3.3 Volt operation 

MU9C4K64-12 Typical Application

·  28 million IPv4 packets per second supports up to 18  Gb Ethernet or 7 OC-48 ATM ports at wire speed
·  Exact match on MAC addresses
·  Processes DA and SA within 190 ns, supporting three ports of 1 Gb or 34 ports of 100 Mb Ethernet at wire speed
·  Mixed mode L3 and L2 single search engine for two ports at 1 Gb or 29 ports of 100 Mb Ethernet at wire speed
·  Directly addresses external RAM containing associated data of any width
·  Hardware control states directly address memory and registers; Instruction and Status registers for optional software control

MU9C4K64-12 Connection Diagram

MU9C4K64-12  Connection Diagram

MU9C4K64-12 datasheet

MU9C4K64-12
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