MVTX2603

• Integrated Single-Chip 10/100/1000 Mbps Ethernet Switch
• 24 10/100 Mbps Autosensing, Fast Ethernet Ports with RMII or Serial Interface (7WS)
• 2 Gigabit Ports with GMII, PCS, 10/100 and stacking (2 G per port) interface options per port
• Serial interface for configuration
• Supports two Frame Buffer Memory domains with SRAM at 100 MHz
• Supports memory size 2 MB, or 4 MB
• For 24+2, two SRAM domains (2 MB or 4 MB) are required.
• For 24+2 stacking (2 G per stacking port), two ZBT domains (2 MB or 4 MB) are required.
• Applies centralized shared memory architecture
• Up to 64K MAC addresses
• Maximum throughput is 6.4 Gbps non-blocking
• High performance packet forwarding (19.047 M packets per second) at full wire speed
• Full Duplex Ethernet IEEE 802.3x Flow Control
• Backpressure flow control for Half Duplex ports
• Supports Ethernet multicasting and broadcasting and flooding control
• Supports per-system option to enable flow control for best effort frames even on QoS-enabled ports
• Load sharing among trunked ports can be based on source MAC and/or destination MAC. The Gigabit trunking group has one more option, based on source port.
• Port Mirroring to a dedicated port or port 23
• Built-in reset logic triggered by system malfunction
• I2C EEPROM for configuration
• Traffic Classification
• 4 transmission priorities for Fast Ethernet ports with 2 dropping levels
• Classification based on:
     - Port based priority
     - VLAN Priority field in VLAN tagged frame
     - DS/TOS field in IP packet
     - UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
• The precedence of the above classifications is programmable
• QoS Support
• Supports IEEE 802.1p/Q Quality of Service with 4 transmission priority queues with delay bounded, strict priority, and WFQ service disciplines
• Provides 2 levels of dropping precedence with WRED mechanism
• User controls the WRED thresholds
• Buffer management: per class and per port buffer reservations
• Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID.
• 3 port trunking groups, one for the 2 Gigabit ports, and two groups for 10/100 ports, with up to 4 10/100 ports per group
• Full set of LED signals provided by a serial interface or 6 LED signals dedicated to Gigabit port status only (without serial interface)
• Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports
• Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports
• Built-In Self Test for internal and external SRAM

The MVTX2603 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 24 ports at 10/100 Mbps, 2 ports at 1000 Mbps. The Gigabit ports can also support 10/100 M and 2 G stacking modes.
The chip supports up to 64 K MAC addresses. The centralized shared memory architecture permits a very high performance packet forwarding rate at up to 9.524 M packets per second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching.

Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate bandwidth of 12.8 Gbps to support full wire speed on all ports simultaneously. In the 24+2 stacking (2 G per stacking port) configuration, 2 ZBT domains are needed.

With delay bounded, strict priority, and/or WFQ transmission scheduling and WRED dropping schemes, the MVTX2603 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The MVTX2603 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range).

The MVTX2603 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports and the other two groups to 10/100 ports, where each 10/100 group can contain up to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The MVTX2603 also supports a persystem option to enable flow control for best effort frames even on QoS-enabled ports.

The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface for connection to SERDES chips. The PCS can be bypassed to provide a GMII interface.

The MVTX2603 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The MVTX2603 is packaged in a 553-pin Ball Grid Array package.