Features: GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 134,217,728 x 1 bit structure
• 4096 equal sectors with 4K byte each
256 equal sectors with 64K byte each
- Any sector can be erased
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 50MHz serial clock (30pF + 1TTL Load)
- Fast program time: 1.4ms/page (typical, 256-byte per page) and 9us/byte (typical)
- Fast erase time: 60ms/sector (4KB per sector), 0.7s/block (64KB per block) and 80s/chip
- Acceleration mode:
- Chip erase time: 50s (typical)
• Low Power Consumption
- Low active read current: 25mA (max.) at 50MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (max.)
- Deep power-down mode 20uA (max.)
• Typical 100,000 erase/program cycle
• 10 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte Device ID
- RES command, 1-byte Device ID
- REMS command, ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO
- Serial Data Output
• WP#/ACC Pin
- Hardware write protection and Program/erase acceleration
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 16-pin SOP (300mil)
- All Pb-free devices are RoHS CompliantPinout
Specifications
| RATING |
VALUE |
| Ambient Operating Temperature |
-40 to 85 for Industrial grade |
| Storage Temperature |
-55 to 125 |
| Applied Output Voltage |
-0.5V to 4.6V |
| Applied Output Voltage |
-0.5V to 4.6V |
| VCC to Ground Potential |
-0.5V to 4.6V |
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns.
4. All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V.
DescriptionThe MX25L12805D is a CMOS 134,217,728 bit serial Flash Memory, which is configured as 16,777,216 x 8 internally. The MX25L12805D features a serial peripheral interface and software protocol allowing operation on a simple 3- wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.
The MX25L12805D provides sequential read operation on whole chip. User may start to read from any byte of the array. While the end of the array is reached, the device will wrap around to the beginning of the array and continuously outputs data until CS# goes high.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, and erase command is executed on sector (4K-byte), or block(64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current.
The MX25L12805D utilizes MXIC's proprietary memory cell which reliably stores memory contents even after 100,000 program and erase cycles.
MX25L12805D Data Sheet
