Features: GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 4M: 4,194,304 x 1 bit structure or 2,097,152 x 2 bits (two I/O read mode) structure or 1,048,576 x 4 bits (four I/O read mode) structure
8M: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two I/O read mode) structure or 2,097,152 x 4 bits (four I/O read mode) structure
• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 40MHz with 8 dummy cycles (30pF+1TTL Load)
- 2 I/O: 40MHz with 4 dummy cycles (30pF+1TTL Load), equivalent to 80MHz
- 4 I/O: 33MHz with 6 dummy cycles (30pF+1TTL Load), equivalent to 132MHz
- Fast program time: 2ms(typ.) and 7ms(max.)/page (256-byte per page)
- Byte program time: 30us (typical)
- Continuously program mode (automatically increase address under word program mode)
- Fast erase time: 90ms (typ.)/sector (4K-byte per sector); 0.8s(typ.) /block (32K-byte per block); 1.5s(typ.) /block (64K-byte per block); 7.5s(typ.) /chip for 4M; 15s(typ.) /chip for 8M
• Low Power Consumption
- Low active read current: 12mA(max.) at 40MHz, 6mA(max.) at 25MHz
- Low active erase/programming current: 22mA (max.)
- Low standby current: 5uA (max.)
• Deep Power Down: 5uA(max.)
• Typical 100,000 erase/program cycles
• 10 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector or block
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- Both REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
• RESET#/HOLD#/SIO3
- Hardware Reset/HOLD/Serial input & Output for 4 x I/O read mode, the pin defaults to be RESET#
• PACKAGE
- 8-land USON (4x4mm) for 4M/8M
- 8-pin SOP (150mil) for 4M/8M
- All Pb-free devices are RoHS CompliantPinout
Specifications
| RATING |
VALUE |
| Ambient Operating Temperature |
-40 to 85 |
| Storage Temperature |
-65 to 150 |
| Applied Input Voltage |
-0.5V to VCC+0.5V |
| Applied Output Voltage |
-0.5V to VCC+0.5V |
| VCC to Ground Potential |
-0.5V to VCC+0.5V |
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V to VCC or -0.5V to GND for period up to 20ns.
DescriptionThe MX25U4035 are 4,194,304 bit serial Flash memory, which is configured as 524,288 x 8 internally. When it is in two or four I/O read mode, the structure becomes 2,097,152 bits x 2 or 1,048,576 bits x 4. The MX25U8035 are 8,388,608 bit serial Flash memory, which is configured as 1,048,576 x 8 internally. When it is in two or four I/O read mode, the structure becomes 4,194,304 bits x 2 or 2,097,152 bits x 4. When it is in two or four I/O read mode, the structure becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. The MX25U4035/MX25U8035 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and RESET#/HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U4035/MX25U8035 provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for Continuously program mode, and erase command is executes on sector (4K-byte), block (32K-byte), or block (64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the MX25U4035. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 5uA DC current.
The MX25U4035/MX25U8035 utilizes MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.
MX25U4035 Data Sheet
