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Part Number: M 67025
Description: The M 67025 is a very low power CMOS dual port static RAM organised as 8192 * 16. The M 67025 is designed to be used as...
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M 67025
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General Description
M 67025 General Description
The M 67025 is a very low power CMOS dual port static RAM organised as 8192 * 16. The M 67025 is designed to be used as a stand-alone 16 bit dual port RAM or as a combination MASTER/SLAVE dual port for 32 bit or more width systems. The MATRA-MHS MASTER/SLAVE dual port approach in memory system applications results in full speed, error free operation without the need of an additional discrete logic.
Master and slave devices provide two independant ports with separate control, address and I/O pins that permit independant, asynchronous access for reads and writes to any location in the memory. An automatic power down feature controlled by CS permits the on-chip circuitry of each port in order to enter a very low stand by power mode.
Using an array of eigh transistors (8T) memory cell and fabricated with the state of the art 0.65 lithography named SCMOS, the M 67025 combines an extremely low standby supply current (typ = 1.0 A) with a fast access time at 20 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 5 W.
For military/space applications that demand superior levels of performance and reliability the M 67025 is processed according to the methods of the latest revision of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
M 67025 Maximum Ratings
Supply voltage (VCC-GND) : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7.0 V
Input or output voltage applied : . . . . . . . . . . . . . . . . . . . . . . . . . . (GND 0.3 V) to (VCC + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to +150
* Notice
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extented periods may affect reliability.
Input or output voltage applied : . . . . . . . . . . . . . . . . . . . . . . . . . . (GND 0.3 V) to (VCC + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to +150
* Notice
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extented periods may affect reliability.
| OPERATING RANGE | OPERATING SUPPLY VOLTAGE | OPERATING TEMPERATURE |
| Military | Vcc = 5 V ± 10 % | 55 to + 125 |
| Industrial | Vcc = 5 V ± 10 % | 40 to + 85 |
| Commercial | Vcc = 5 V ± 10 % | 0 to + 70 |
M 67025 Features
Fast access time : 20/25/30/35/45/55 ns
Wide temperature range : 55 °C to +125 °C
67025 L low power
67025 V very low power
Separate upper byte and lower byte control for multiplexed bus compatibility
Expandable data bus to 32 bits or more using master/slave chip select when using more than one device
On chip arbitration logic
Versatile pin select for master or slave :
M/S = H for busy output flag on master
M/S = L for busy input flag on slave
INT flag for port to port communication
Full hardware support of semaphore signaling between ports
Fully asynchronous operation from either port
Battery back-up operation : 2 V data retention
TTL compatible
Single 5 V ± 10 % power supply
For 3.3 V version, please consult sales
Wide temperature range : 55 °C to +125 °C
67025 L low power
67025 V very low power
Separate upper byte and lower byte control for multiplexed bus compatibility
Expandable data bus to 32 bits or more using master/slave chip select when using more than one device
On chip arbitration logic
Versatile pin select for master or slave :
M/S = H for busy output flag on master
M/S = L for busy input flag on slave
INT flag for port to port communication
Full hardware support of semaphore signaling between ports
Fully asynchronous operation from either port
Battery back-up operation : 2 V data retention
TTL compatible
Single 5 V ± 10 % power supply
For 3.3 V version, please consult sales
M 67025 Connection Diagram
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- · EPCS4SI8
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- · UTC2411
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- ·(M5M410092B)
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- LOW FORWARD VOLTAGE DROP
- 29515 KB
- ·0001.2501.PT
- Fuse
- 40400 KB
- ·0001.2501.TR
- Fuse
- 40400 KB
- ·0001.2502.PT
- Fuse
- 40400 KB
- ·0001.2502.TR
- Fuse
- 40400 KB
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