NB4L339

The NB4L339 is a multi−function Clock generator featuring a 2:1 Clock multiplexer front end and simultaneously outputs a selection of four different divide ratios from its four divider blocks; ÷1/÷2/÷4/÷8. One divide block has a choice of ÷1 or ÷ 2.

The output of each NB4L339 divider block is fanned−out to two identical differential LVPECL copies of the selected clock. All outputs provide standard LVPECL voltage levels when externally terminated with a 50−ohm resistor to VCC − 2 V.
The differential Clock inputs incorporate internal 50− termination resistors and will accept LVPECL, CML or LVDS logic levels.

The common Output Enable pin (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the NB4L339 is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip−flop is clocked on the falling edge of the input clock. Therefore, all associated specification limits are referenced tothe negative edge of the clock input.

NB4L339  is housed in a 5x5 mm 32 pin QFN package.