Features: • Guaranteed Input Clock Frequency up to 1.0 GHz
• Guaranteed Input Data Rate up to 1.5 Gb/s
• 490 ps Maximum Propagation Delay
• 1.0 ps Maximum RMS Jitter
• 180 ps Maximum Rise/Fall Times
• Single Power Supply; VCC = 3.3 V ±10%
• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
• GND + 50 mV to VCC − 50 mV VCMR RangePinout
Specifications
|
Symbol |
Parameter |
Condition 1 |
Condition 2 |
Rating |
Unit |
|
VCC |
Positive Power Supply |
GND = 0 V |
|
3.8 |
V |
|
VI |
Positive Input |
GND = 0 V |
VI = VCC |
3.8 |
V |
|
IIN |
Input Current Through RT (50 Resistor) |
Static
Surge |
|
35
70 |
mA
mA |
|
IOSC |
Output Short Circuit Current
Line−to−Line (Q to Q )
Line−to−End (Q or Q to GND) |
Q or Q to GND
Q to Q |
Continuous
Continuous |
12
24 |
mA |
|
TA |
Operating Temperature Range |
Micro 10 |
|
−40 to +85 |
|
|
Tstg |
Storage Temperature Range |
|
|
−65 to +150 |
|
|
JA |
Thermal Resistance (Junction−to−Ambient) (Note 2) |
0 lfpm
500 lfpm |
Micro 10
Micro 10 |
177
132 |
/W
/W |
|
JC |
Thermal Resistance (Junction−to−Case) |
1S2P (Note 4) |
Micro 10 |
40 |
/W |
|
Tsol |
Wave Solder Pb
Pb−Free |
<3 Sec @ 248°C
<3 Sec @ 260°C |
|
265
265 |
|
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device unctional operation is not implied, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power).
DescriptionNB4N855S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 1.5 Gb/s or 1.0 GHz, respectively. This device is pin−for−pin plug in compatible to the SY55855V in a 3.3 V applications.
The NB4N855S has a wide input common mode range of GND + 50 mV to VCC − 50 mV. This feature is ideal for translating differential or single−ended data or clock signals to 350 mV typical LVDS output levels.
The device is offered in a small 10 lead MSOP package. NB4N855S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements.Application notes, models, and support documentation are available at www.onsemi.com.
NB4N855S Data Sheet
