NJU25005

The NJU25005 is a digital surround processor which decodes Dolby Pro Logic surround signals and generates simulated surround sound.It consists of a 24-bit fixed point digit signal processor,internal memory(ROM and RAM), interface circuits, and other logic necessary to implement a true digital surround sound decoder.The NJU25005 incorporates all functions of dolby pro logic using high quality digital signal processing techniques.It can also easily create various kinds of surround sound in the simulated surround mode, generating soundfields by using optional external memory to digitally implement larger delays.

Features of the NJU25005 are:(1)24-bit fixed point---digital signal processing; (2)on-chip digital delay,30ms max; (3)no external memory required; (4)dolby 3 stereo mode; (5)internal auto input balance; (6)serial or parallel command control interface; (7)operates from a single +5V supply; (8)evaluation board available; (9)no DSP design required; (10)mono-ta-stereo synthesis; (11)16- or 18-bit external A/D and D/A converters.

The absolute maximum ratings of the NJU25005 can be summarized as:(1)supply voltage Vdd:-0.3 to 7V;(2)storage temperature:-55 to +125;(3)operating temperature:-20 to 70 ;(4)input,output pin voltage:-0.3 to Vdd+0.3V.The audio stops when NJU25005 receives a system state download command, when simulated surround mode coefficients are downloaded, or when the noise sequencer is turned on.All other commands take immediate effect without interruption in the audio. Only one command should be sent from the microprocessor per UR period.The DSP in the NJU25005 spends most of the time processing audio, during which time microprocessor interrupts are disabled. Writing to the MPU interface sets an interrupt request flag inside the chip and holds the data in a register which is read as soon as the interrupt can be serviced.For the output serial data, the NJU25005 is considered the source and the D/A's are considered the destination.The default interface setting is for data to be clocked out of SDD on the falling edge of SCKO so that the D/A clocks data in on the rising edge.This can be changed as well independently of the input and interface mode using the SCKO bit in the system download command.