NM24C05

Features:

 Extended operating voltage 2.7V 5.5V
  400 KHz clock frequency (F) at 2.7V - 5.5V
  200A active current typical
     10A standby current typical
     1A standby current typical (L)
      0.1A standby current typical (LZ)
  IIC compatible interface
        Provides bi-directional data transfer protocol
  Schmitt trigger inputs
  Sixteen byte page write mode
        Minimizes total write time per byte
  Self timed write cycle
     Typical write cycle time of 6ms
  Hardware Write Protect for upper half (NM24C05 only)
  Endurance: 1,000,000 data changes
  Data retention greater than 40 years
  Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
  Available in three temperature ranges
        - Commercial: 0° to +70°C
        - Extended (E): -40° to +85C
        - Automotive (V): -40° to +125°C


Pinout




Specifications

Ambient Storage Temperature            65 to +150
All Input or Output Voltages
        with Respect to Ground               6.5V to 0.3V
Lead Temperature
         (Soldering, 10 seconds)              +300
ESD Rating                                           2000V min.


Description

The NM24C04/05 devices are 4096 bits of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the Standard IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements.

The upper half (upper 2Kbit) of the memory of the NM24C05 can be write protected by connecting the WP pin to V_CC. This section of memory then becomes unalterable unless WP is switched to VSS.

This communications protocol of NM24C05 uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). The Standard IIC protocol allows for a maximum of 16K of EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the memory as the application of NM24C05 requires with any combination of EEPROMs. In order to implement higher EEPROM memory densities on the IIC bus, the Extended IIC protocol must be used. (Refer to the NM24C32 or NM24C65 datasheets for more information.)

Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption.