NT5DS32M16BG-6K

The NT5DS32M16BG-6K is a kind of 512Mb DDR SDRAM. The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. Besides, it uses a double-data-rate architecture to achieve high-speed operation.

There are some features as follows: (1) DDR 512M bit, die B, based on 110nm design rules; (2) double data rate architecture: two data transfers per clock cycle; (3) bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver; (4) DQS is edge-aligned with data for reads and is center-aligned with data for writes; (5) differential clock inputs (CK and CK); four internal banks for concurrent operation; (6) data mask (DM) for write data; DLL aligns DQ and DQS transitions with CK transitions; (7) commands entered on each positive CK edge; (8) data and data mask referenced to both edges of DQS; (9) burst lengths: 2, 4, or 8; (10) auto Precharge option for each burst access; (11) auto refresh and self refresh modes; (12) 7.8s maximum average periodic refresh interval; (13) 2.5 V (SSTL_2 compatible) I/O.

What comes next is about the absolute maximum ratings. (1): VIN, VOUT (voltage on I/O pins relative to VSS) is from -0.5 to VDDQ+0.5 V;  (2): VIN (voltage on inputs relative to VSS) is from -0.5 to +3.6 V; (3): VDD (voltage on VDD supply relative to VSS) is from -0.5 to +3.6 V; (4): VDDQ (voltage on VDDQ supply relative to VSS) is from -0.5 to +3.6 V; (5): TA (operating temperature (ambient)) is from 0 to +70; (6): TSTG (storage temperature (plastic)) is from -55 to +150; (7): PD (power dissipation) is 1.0 W; (8): IOUT (short circuit output current) is 50 mA.