MFG:ORCA Package Cooled:BGA D/C:05+
MFG: ORCA
Package Cooled: BGA
D/C: 05+
Description: The ATM UTOPIA Slave Core from Modelware† implements, in modular VHDL, the ATM forum's UTOPIA Le...
The ATM UTOPIA Slave Core from Modelware† implements, in modular VHDL, the ATM forum's UTOPIA Level 1 and Level 2 specifications.
The core interfaces to the application (e.g., ATM physical or adaptation layer) via a generic FIFO-like access interface and to the ATM layer via a UTOPIA Level 1 or Level 2 interface (Figure 1). The core uses internal FIFOs for cell buffering and timing transfer between the application and the ATM layer.
The core (using 18-bit internal FIFOs) operates at 50 MHz in an OR2T15A-6 or an OR3T55-7 ORCA FPGA.
OR3C55
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