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Part Number: OR3TP12

 

 

 

 

Description: The following sections describe the operation of the embedded PCI bus core interface.


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OR3TP12 General Description


The following sections describe the operation of the embedded PCI bus core interface.

OR3TP12 Maximum Ratings

Parameter

Symbol

Min

Max

Unit

Storage Temperature

Tstg

65

150

Supply Voltage with Respect to Ground

VDD

0.5

7.0

V

Input Signal with Respect to Ground

-

0.5

VDD + 0.3*

V

Signal Applied to High-impedance Output

-

0.5

VDD + 0.3*

V

Maximum Package Body Temperature

-

-

220

 

* For PCI bus signals used for 5 V signaling and FPGA inputs used as 5 V tolerant, the maximum value is 5.8 V.

OR3TP12 Features

`The Series 3 also provides system-level functionality by means of its dual-use microprocessor interface (MPI) and its innovative PCM. These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today's high-speed systems. Since these and all other Series 3T features are available in every Series 3+ FPSC, they can also interface to the embedded core providing for easier system integration.

OR3TP12 datasheet

OR3TP12
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