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Part Number: OR4E10
Description: This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user- programmabl...
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OR4E10
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DataSheet
General Description
OR4E10 General Description
This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user- programmable
I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled
after configuration.
OR4E10 Maximum Ratings
| Parameter | Symbol | Min | Max | Unit |
| Storage Temperature | Tstg | 65 | 150 | |
| Power Supply Voltage with Respect to Ground | VDD3 | - | 4.2 | V |
| VDD15 | - | 2 | V | |
| Input Signal with Respect to Ground | - | VSS 0.3 | VDDIO + 0.3 | V |
| Signal Applied to High-impedance Output | - | VSS 0.3 | VDDIO + 0.3 | V |
| Maximum Package Body Temperature | - | - | 220 |
OR4E10 Features
` High-performance platform design.
- 0.13 m seven-level metal technology.
- Internal performance of >250 MHz (four logic levels).
- I/O performance of >416 MHz for all user I/Os.
- Over 1.5 million usable system gates.
- Meets multiple I/O interface standards.
- 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
- Embedded block RAM (EBR) for onboard storage and buffer needs.
- Built-in system components including an internal system bus, eight PLLs, and microprocessor interface.
` Traditional I/O selections.
- LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os.
- Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.
- Individually programmable drive capability. 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.
- Two slew rates supported (fast and slew-limited).
- Fast-capture input latch and input flip-flop (FF)/ latch for reduced input setup time and zero hold time.
- Fast open-drain drive capability.
- Capability to register 3-state enable signal.
- Off-chip clock drive capability.
- Two-input function generator in output path.
` New programmable high-speed I/O.
- Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), zero-bus turn-around (ZBT*), and double data rate (DDR).
- Double-ended: LDVS, bused-LVDS, LVPECL.
- Customer defined: Ability to substitute arbitrary standard-cell I/O to meet fast moving standards.
` New capability to (de)multiplex I/O signals.
- New DDR on both input and output at rates up to 311 MHz (622 MHz effective rate).
- Used to implement emerging RapidIO† backplane interface specification.
- New 2x and 4x downlink and uplink capability per I/O (i.e., 104 MHz internal to 416 MHz I/O).
` Enhanced twin-quad programmable function unit (PFU).
- Eight 16-bit look-up tables (LUTs) per PFU.
- Nine user registers per PFU, one following each LUT and organized to allow two nibbles to act independently, plus one extra for arithmetic carry/borrow operations.
* ZBT is a trademark of Integrated Device Technologies Inc.
†RapidIO is a trademark of Motorola, Inc.
- 0.13 m seven-level metal technology.
- Internal performance of >250 MHz (four logic levels).
- I/O performance of >416 MHz for all user I/Os.
- Over 1.5 million usable system gates.
- Meets multiple I/O interface standards.
- 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance.
- Embedded block RAM (EBR) for onboard storage and buffer needs.
- Built-in system components including an internal system bus, eight PLLs, and microprocessor interface.
` Traditional I/O selections.
- LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os.
- Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance.
- Individually programmable drive capability. 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source.
- Two slew rates supported (fast and slew-limited).
- Fast-capture input latch and input flip-flop (FF)/ latch for reduced input setup time and zero hold time.
- Fast open-drain drive capability.
- Capability to register 3-state enable signal.
- Off-chip clock drive capability.
- Two-input function generator in output path.
` New programmable high-speed I/O.
- Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), zero-bus turn-around (ZBT*), and double data rate (DDR).
- Double-ended: LDVS, bused-LVDS, LVPECL.
- Customer defined: Ability to substitute arbitrary standard-cell I/O to meet fast moving standards.
` New capability to (de)multiplex I/O signals.
- New DDR on both input and output at rates up to 311 MHz (622 MHz effective rate).
- Used to implement emerging RapidIO† backplane interface specification.
- New 2x and 4x downlink and uplink capability per I/O (i.e., 104 MHz internal to 416 MHz I/O).
` Enhanced twin-quad programmable function unit (PFU).
- Eight 16-bit look-up tables (LUTs) per PFU.
- Nine user registers per PFU, one following each LUT and organized to allow two nibbles to act independently, plus one extra for arithmetic carry/borrow operations.
* ZBT is a trademark of Integrated Device Technologies Inc.
†RapidIO is a trademark of Motorola, Inc.
OR4E10
PDF/DataSheet Download
- Datasheet: OR4E10
- File Size: 3206532 KB
- Manufacturer: AGERE [Agere Systems]
- Click here to Download
- ·OR4E2
- AGERE [Agere Systems]
- Field-Programmable Gate Arrays
- 3206532 KB
- ·OR4E4
- AGERE [Agere Systems]
- Field-Programmable Gate Arrays
- 3206532 KB
- ·OR4E6
- AGERE [Agere Systems]
- Field-Programmable Gate Arrays
- 3206532 KB
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