P3Z22V10

The P3Z22V10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Philips Semiconductors has used their FZPE design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. P3Z22V10 results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 5V operation, Philips Semiconductors offers the P5Z22V10 that offers high speed and low power in a 5V implementation.

The P3Z22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. P3Z22V10 has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.