P80C51 General Description
P80C51 Features
1.1 P80C51 CPU core
` 80C51 8-bit CPU
` 64-kbyte Multiple Programming ROM (MTP ROM)
` Two 16-bit timer/event counters
` Crystal oscillator for system clock (up to 12 MHz)
` 12 source, 12 vector interrupt structure with two priority levels
` Enhanced architecture with:
Non-page orientated instructions
Direct addressing
Four 8-byte RAM register banks
Stack depth up to 128 bytes
Multiply, divide, subtract and compare instructions.
1.2 P8xCx66 family
` ROM/RAM: see Table 1
` Pulse Width Modulated (PWM) outputs:
One 14-bit PWM output for Voltage Synthesized Tuning (VST)
Eight 7-bit PWM outputs for analog controls.
` 3 Analog-to-Digital (ADC) inputs with 4-bit DAC and comparator
` LED driver port:
All I/O port lines with 10 mA LED drive capability (VO <1.0 V)
Up to 5 LEDs can be driven at any one time.
` Serial I/O:
Multi-master I2C-bus interface
Maximum I2C-bus frequency 400 kHz.
` Watchdog timer
` Improved EMC measures and slope controlled I/Os
` OSD functions:
Programmable VSYNC and HSYNC active levels
Display RAM: 192 ´ 12 bits
Display character fonts: 128 (126 customer fonts plus 2 reserved codes)
63 vertical starting positions controlled by software
110 horizontal starting positions controlled by software
Character size: 4 different character sizes on a line-by-line basis
Character matrix: 12 ´ 18 with no spacing between characters
Foreground colours: 8 on a character-by-character basis
Background/shadowing modes: two primary modes -TV mode and Frame mode on a frame basis. Each primary mode has four sub-modes on a line basis:
Sub-mode 1: Superimpose (no background)
Sub-mode 2: North-West shadowing
Sub-mode 3: Box background
Sub-mode 4: Border shadowing
Background colours: 8 on a word-by-word basis, available in all four sub-modes
Display RAM starting address is programmable; fast switching between banks of display (RAM) characters is possible through software control
HSYNC driven PLL for OSD clock (4 to 12 MHz)
Character blinking ratio: 1 : 1
Character blinking frequency: programmable using fVSYNC divisors of 32 and 64, on a character basis
Flexible display format using the Carriage Return code and the Space codes
Display RAM address post incremented each time new data is written into RAM
Vertical jitter cancelling circuit to avoid unstable VSYNC leading edge mismatch with HSYNC signal
OSD meshing.
` Power-on reset
` Packages: SDIL42 (PLCC68 for piggy-back only)
` Operating voltage: 4.5 to 5.5 V
` Operating temperature: -20 to +70 °C
` System clock frequency: 4 to 12 MHz
` OSD clock frequency: 4 to 12 MHz.
Map list: ABCDEFGHIJKLMNOPQRSTUVWXYZ 0123456789All