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Part Number: PC7447A
Description: The PC7447A host processor is a high-performance, low-power, 32-bit implementa-tions of the PowerPC Re...
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PC7447A
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General Description
PC7447A General Description
The PC7447A host processor is a high-performance, low-power, 32-bit implementa-tions of the PowerPC Reduced Instruction Set Computer (RISC) architecture combined with a full 128-bit implementation of Motorola®'s AltiVec™ technology.
This microprocessor is ideal for leading-edge embedded computing and signal pro-cessing applications. The PC7447A features 512 KB of on-chip L2 cache. The PC7447A microprocessor has no backside L3 cache, allowing for a smaller package designed as a pin-for-pin replacement for the PC7447 microprocessor. This device benefits from a silicon-on-insulator (SOI) CMOS process technology, engineered to help deliver tremendous power savings without sacrificing speed. A low-power version of the PC7447A microprocessor is also available.
Figure 1 shows a block diagram of the PC7447A. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multi-media unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to the main memory and other system resources.
Note that the PC7447A is a footprint-compatible, drop-in replacement in a PC7447 application if the core power supply is 1.3V.
PC7447A Maximum Ratings
| Symbol | Characteristic |
MaximumValue |
Unit | |
| VDD(2) AVDD(2) OVDD(3)(4) OVDD(3)(5) VIN(6)(7) VIN TSTG |
Core supply voltage PLL supply voltage Processor bus supply voltage Input voltage Storage temperature range |
BVSEL = 0 BVSEL = HRESET or OVDD Processor bus JTAG signals |
-0.3 to 1.60 -0.3 to 1.60 -0.3 to 1.95 -0.3 to 2.7 -0.3 to OVDD + 0.3 -0.3 to OVDD + 0.3 -55 to 150 |
V V V V V V °C |
2.Caution: VDD/AVDD must not exceed OVDD by more than 1V during normal operation; this limit may be exceeded for a maxi-mum of 20 ms during the power-on reset and power-down sequences.
3.Caution: OVDD must not exceed VDD/AVDD by more than 2V during normal operation; this limit may be exceeded for a maxi-mum of 20 ms during the power-on reset and power-down sequences.
4.BVSEL must be set to 0, such that the bus is in 1.8V mode.
5.BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.
6.Caution: VIN must not exceed OVDD by more than 0.3V at any time including during power-on reset.
7.VIN may overshoot/undershoot to a voltage and for a maximum duration shown in Figure 3 on page 10.
PC7447A Features
•3000 Dhrystone 2.1 MIPS at 1.3 GHz
•Selectable Bus Clock (30 CPU Bus Dividers up to 28x)
•Selectable MPx/60x Interface Voltage (1.8V, 2.5V)
•PD Typically 18W at 1.33 GHz at VDD = 1.3V; 8.0W at 1 GHz at VDD = 1.1V Full Operating Conditions
•Nap, Doze and Sleep Power Saving Modes
•Superscalar (Four Instructions Fetched Per Clock Cycle)
•4 GB Direct Addressing Range
•Virtual Memory: 4 Hexabytes (252)
•64-bit Data and 36-bit Address Bus Interface
•Integrated L1: 32 KB Instruction and 32 KB Data Cache
•Integrated L2: 512 KB
•11 Independent Execution Units and 3 Register Files
•Write-back and Write-through Operations
•fINT Max = 1.33 GHz (1.42 GHz to be Confirmed)
•fBUS Max = 133 MHz/166 MHz
•Selectable Bus Clock (30 CPU Bus Dividers up to 28x)
•Selectable MPx/60x Interface Voltage (1.8V, 2.5V)
•PD Typically 18W at 1.33 GHz at VDD = 1.3V; 8.0W at 1 GHz at VDD = 1.1V Full Operating Conditions
•Nap, Doze and Sleep Power Saving Modes
•Superscalar (Four Instructions Fetched Per Clock Cycle)
•4 GB Direct Addressing Range
•Virtual Memory: 4 Hexabytes (252)
•64-bit Data and 36-bit Address Bus Interface
•Integrated L1: 32 KB Instruction and 32 KB Data Cache
•Integrated L2: 512 KB
•11 Independent Execution Units and 3 Register Files
•Write-back and Write-through Operations
•fINT Max = 1.33 GHz (1.42 GHz to be Confirmed)
•fBUS Max = 133 MHz/166 MHz
PC7447A
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- Datasheet: PC7447A
- File Size: 1437688 KB
- Manufacturer: atmel
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