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Description: The PC755 and PC745 PowerPC® microprocessors are high-performance, lowpower, 32-bit implementation...


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PC745 General Description


The PC755 and PC745 PowerPC® microprocessors are high-performance, lowpower, 32-bit implementations of the PowerPC Reduced Instruction Set Computer (RISC) architecture, especially enhanced for embedded applications.

The PC755 and PC745 microprocessors differ only in that the PC755 features an enhanced, dedicated L2 cache interface with on-chip L2 tags. The PC755 is a drop-in replacement for the award winning PowerPC 750™ microprocessor and is footprint and user software code compatible with the MPC7400 microprocessor with AltiVec™ technology. The PC745 is a drop-in replacement for the PowerPC 740™ microprocessor and is also footprint and user software code compatible with the PowerPC 603e™ microprocessor. PC755/745 microprocessors provide on-chip debug support and are fully JTAG-compliant.

The PC745 microprocessor is pin compatible with the TSPC603e family.

PC745 Maximum Ratings

Characteristic Symbol Maximum Value Unit
Core supply voltage(4) VDD -0.3 to 2.5 V
PLL supply voltage(4) AVDD -0.3 to 2.5 V
L2 DLL supply voltage(4) L2AVDD -0.3 to 2.5 V
Processor bus supply voltage(3) OVDD -0.3 to 3.6 V
L2 bus supply voltage(3) L2OVDD -0.3 to 3.6 V
Input voltage Processor bus(2)(5) Vin -0.3 to OVDD + 0.3V V
  L2 Bus(2)(5) Vin -0.3 to L2OVDD + 0.3V V
  JTAG Signals Vin -0.3 to 3.6 V
Storage temperature range Tstg -65 to 150 °C
Rework Temperature Trwk 220 °C

Notes:
1. Functional and tested operating conditions are given in Table 5. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: VIN must not exceed OVDD or L2OVDD by more than 0.3V at any time including during power-on reset.
3. Caution: L2OVDD /OVDD must not exceed VDD/AVDD /L2AVDD  by more than 1.6V during normal operation. During power-on reset and power-down sequences, L2OVDD/OVDD may exceed VDD/AVDD /L2AVDD by up to 3.3V for up to 20 ms, or by 2.5V for up to 40 ms. Excursions beyond 3.3V or 40 ms are not supported.
4. Caution: VDD/AVDD /L2AVDD  must not exceed L2OVDD/OVDD  by more than 0.4V during normal operation. During power-on reset and power-down sequences, VDD/AVDD/L2AVDD may exceed L2OVDD /OVDD  by up to 1.0V for up to 20 ms, or by 0.7V for up to 40 ms. Excursions beyond 1.0V or 40 ms are not supported.
5. This is a DC specifications only. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 5.

PC745 Features

• 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz (PC755)
• 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745)
• 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)
• Selectable Bus Clock (12 CPU Bus Dividers up to 10x)
• PD Typical 6.4W at 400 MHz, Full Operating Conditions
• Nap, Doze and Sleep Modes for Power Savings
• Superscalar (3 Instructions per Clock Cycle) Two Instruction + Branch
• 4 Beta Byte Virtual Memory, 4-GByte of Physical Memory
• 64-bit Data and 32-bit Address Bus Interface
• 32-KB Instruction and Data Cache
• Six Independent Execution Units
• Write-back and Write-through Operations
• fINT max = 400 MHz (TBC)
• fBUS max = 100 MHz
• Voltage I/O 2.5V/3.3V; Voltage Int 2.0V

PC745 datasheet

PC745
PDF/DataSheet Download

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