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Part Number: PC745B
Description: The PC755B and PC745B PowerPC® microprocessors are high-performance, lowpower, 32-bit i...
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PC745B
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General Description
PC745B General Description
The PC755B and PC745B PowerPC® microprocessors are high-performance, lowpower, 32-bit implementations of the PowerPC Reduced Instruction Set Computer (RISC) architecture, especially enhanced for embedded applications.
The PC755B and PC745B microprocessors differ only in that the PC755B features an enhanced, dedicated L2 cache interface with on-chip L2 tags. The PC755B is a dropin replacement for the award winning PowerPC 750™microprocessor and is footprint and user software code compatible with the MPC7400 microprocessor with AltiVec™ technology. The PC745B is a drop-in replacement for the PowerPC 740™ microprocessor and is also footprint and user software code compatible with the PowerPC 603e™ microprocessor. PC755B/745B microprocessors provide on-chip debug support and are fully JTAG-compliant.
The PC745B microprocessor is pin compatible with the TSPC603e family.
PC745B Maximum Ratings
| Characteristic | Symbol | Maximum Value | Unit | |
| Core supply voltage(4) | VDD | -0.3 to 2.5 | V | |
| PLL supply voltage(4) | AVDD | -0.3 to 2.5 | V | |
| L2 DLL supply voltage(4) | L2AVDD | -0.3 to 2.5 | V | |
| Processor bus supply voltage(3) | OVDD | -0.3 to 3.6 | V | |
| L2 bus supply voltage(3) | L2OVDD | -0.3 to 3.6 | V | |
| Input voltage | Processor bus(2)(5) | Vin | -0.3 to OVDD + 0.3V | V |
| L2 Bus(2)(5) | Vin | -0.3 to L2OVDD + 0.3V | V | |
| JTAG Signals | Vin | -0.3 to 3.6 | V | |
| Storage temperature range | Tstg | -55 to 150 | °C | |
Notes: 1. Functional and tested operating conditions are given in Table 4. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
2. Caution: VIN must not exceed OVDD or L2OVDD by more than 0.3V at any time including during power-on reset.
3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 1.6V during normal operation; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.
4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4V during normal operation; this limit may beexceeded for a maximum of 20 ms during power-on reset and power-down sequences.
5. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
PC745B Features
18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz (PC755B)
15.7SPECint95, 9SPECfp95 at 350 MHz (PC745B)
733 MIPS at 400 MHz (PC755B) at 641 MIPS at 350 MHz (PC745B)
Selectable Bus Clock (12 CPU Bus Dividers up to 10x)
PD Typical 6.4W at 400 MHz, Full Operating Conditions.
Nap, Doze and Sleep Modes for Power Savings
Superscalar (3 Instructions per Clock Cycle) Two Instruction + Branch
4 Beta Byte Virtual Memory, 4-GByte of Physical Memory
64-bit Data and 32-bit Address Bus Interface
32-KB Instruction and Data Cache
Six Independent Execution Units
Write-back and Write-through Operations
fINTmax = 400 MHz (TBC)
fBUS max = 100 MHz
Voltage I/O 2.5V/3.3V; Voltage Int 2.0V
15.7SPECint95, 9SPECfp95 at 350 MHz (PC745B)
733 MIPS at 400 MHz (PC755B) at 641 MIPS at 350 MHz (PC745B)
Selectable Bus Clock (12 CPU Bus Dividers up to 10x)
PD Typical 6.4W at 400 MHz, Full Operating Conditions.
Nap, Doze and Sleep Modes for Power Savings
Superscalar (3 Instructions per Clock Cycle) Two Instruction + Branch
4 Beta Byte Virtual Memory, 4-GByte of Physical Memory
64-bit Data and 32-bit Address Bus Interface
32-KB Instruction and Data Cache
Six Independent Execution Units
Write-back and Write-through Operations
fINTmax = 400 MHz (TBC)
fBUS max = 100 MHz
Voltage I/O 2.5V/3.3V; Voltage Int 2.0V
pc745b
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This document is primarily concerned with the PowerPC™ PC7457; however, unless otherwise noted, all information here also applies to the PC7447. The PC7457 and PC7447 are implementations of the PowerPC microprocessor family of reduced instruction set c...
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