PCI2050A

This data sheet for PCI2050A lists only enhancements to PCI2050 and must be used in conjunction with PCI2050, PCI-to-PCI bridge, data manual (Literature number SCPS053A)

The Texas Instruments PCI2050A PCI-to-PCI bridge provides a high performance connection path between two peripheral component interconnect (PCI) buses operating at a maximum bus frequency of 66-MHz. Transactions occur between masters on one and targets on another PCI bus, and the PCI2050A allows bridged transactions to occur concurrently on both buses. The bridge supports burst mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.

The PCI2050A bridge is compliant with the PCI local bus specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per extension slot by creating hierarchical buses. The PCI2050A provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external bus arbiter.

The CompactPCI hot-swap extended PCI capability makes the PCI2050A an ideal solution for multifunction compact PCI cards and adapting single function cards to hot-swap compliance.

The PCI2050A bridge is compliant with PCI-to-PCI bridge specification 1.1. The PCI2050A provides compliance for PCI Power Management 1.0 and 1.1. The PCI2050A has been designed to lead the industry in power consumption and data throughput. An advanced CMOS process achieves low system power consumption while operating at PCI clock rates up to 66-MHz.