PCI7402ZHK

· PC Card Standard 8.1 Compliant
· PCI Bus Power Management Interface Specification 1.1 Compliant
· Advanced Configuration and Power Interface (ACPI) Specification 2.0 Compliant
· PCI Local Bus Specification Revision 2.3 Compliant
· Windows Logo Program Compliant
· PCI Bus Interface Specification for PCI-to-CardBus Bridges
· Fully Compliant with Provisions of IEEE Std 1394-1995 for a High-Performance Serial Bus and IEEE Std 1394a-2000
· Fully Compliant with 1394 Open Host Controller Interface Specification 1.1
· 1.5-V Core Logic and 3.3-V I/O Cells with Internal Voltage Regulator to Generate 1.5-V Core VCC
· Universal PCI Interfaces Compatible with 3.3-V and 5-V PCI Signaling Environments
· Supports PC Card or CardBus with Hot Insertion and Removal
· Supports 132-MBps Burst Transfers to Maximize Data Throughput on Both the PCI Bus and the CardBus
· Supports Serialized IRQ with PCI Interrupts
· Programmable Multifunction Terminals
· Many Interrupt Modes Supported
· Serial ROM Interface for Loading Subsystem ID and Subsystem Vendor ID
· ExCA-Compatible Registers Are Mapped in Memory or I/O Space
· Intel 82365SL-DF Register Compatible
· Supports Ring Indicate, SUSPEND, and PCI CLKRUN Protocols
· Provides VGA/Palette Memory and I/O, and Subtractive Decoding Options, LED Activity Terminals
· Fully Interoperable with FireWire^TM and i.LINK^TM Implementations of IEEE Std 1394
· Compliant with Intel Mobile Power Guideline 2000
· Full IEEE Std 1394a-2000 Support Includes:
Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation,Arbitration Acceleration, Fly-By Concatenation, and Port Disable/Suspend/Resume
· Power-Down Features to Conserve Energy in Battery-Powered Applications Include:
Automatic Device Power Down During Suspend, PCI Power Management for Link-Layer, and Inactive Ports Powered Down, Ultralow-Power Sleep Mode
· Two IEEE Std 1394a-2000 Fully Compliant Cable Ports at 100M Bits/s, 200M Bits/s,and 400M Bits/s
· Cable Ports Monitor Line Conditions for Active Connection to Remote Node
· Cable Power Presence Monitoring
· Separate Cable Bias (TPBIAS) for Each Port
· Physical Write Posting of up to Three Outstanding Transactions
· PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency
· External Cycle Timer Control for Customized Synchronization
· Extended Resume Signaling for Compatibility with Legacy DV Components

Supply voltage range, VR_PORT . . . . . . . . . −0.2 V to 2.2 V
AVDD_33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
VDDPLL_15 . . . . . . . . . . . . . . . . . . . . . .   −0.5 V to 1.836 V
VDDPLL_33 . . . . . . . . . . . . . . . . . . . . . . . . . .  −0.3 V to 4 V
VCCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
SC_VCC_5V . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Clamping voltage range, VCCP and VCCCB . . . . . . . −0.5 V to 6 V
Input voltage range, VI: PCI, CardBus, PHY, SC, miscellaneous . . −0.5 V to VCC + 0.5 V
Output voltage range, VO: PCI, CardBus, PHY, SC, miscellaneous .−0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 3) . . . . . . .  ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 4) . . . . .±20 mA
Human Body Model (HBM) ESD performance . . . . . . . . . 1500 V
Operating free-air temperature, TA . . . . . . . . . . .0°C to 70°C
Storage temperature range, Tstg . . . . . . . .  −65°C to 150°C
Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . .  150°C
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 3. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals and miscellaneous terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to CardBus VCC. The limit specified applies for a dc condition.
4. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals and miscellaneous terminals are measured with respect to VCCP instead of VCC. PC Card terminals are measured with respect to CardBus VCC. The limit specified applies for a dc condition.