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Part Number: PD45128841-T
Description: The PD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access me...
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PD45128841-T
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General Description
PD45128841-T General Description
The PD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 * 4 * 4, 4,194,304 * 8 * 4, 2,097,152 * 16 * 4 (word * bit * bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
PD45128841-T Maximum Ratings
|
Parameter |
Symbol |
Condition |
Rating |
Unit |
| Voltage on power supply pin relative to GND |
VCC, VCCQ |
-0.5 to +4.6 |
V | |
| Voltage on any pin relative to GND |
VT |
-0.5 to +4.6 |
V | |
| Short circuit output current |
IO |
50 |
mA | |
| Power dissipation |
PD |
1 |
W | |
| Operating ambient temperature |
TA |
-20 to + 70 |
| |
| Storage temperature |
Tstg |
-55 to + 125 |
|
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
PD45128841-T Features
· Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
· Pulsed interface
· Possible to assert random column address in every cycle
· Quad internal banks controlled by BA0(A13) and BA1(A12)
· Byte control (×16) by LDQM and UDQM
· Programmable Wrap sequence (Sequential / Interleave)
· Programmable burst length (1, 2, 4, 8 and full page)
· Programmable /CAS latency (2 and 3)
· Ambient temperature (TA): -20 to + 85°C
· Automatic precharge and controlled precharge
· CBR (Auto) refresh and self refresh
· ×4, ×8, ×16 organization
· Single 3.3 V ± 0.3 V power supply
· LVTTL compatible inputs and outputs
· 4,096 refresh cycles / 64 ms
· Burst termination by Burst stop command and Precharge command
PD45128841-T Connection Diagram
PD45128841-T
PDF/DataSheet Download
- Datasheet: PD45128841-T
- File Size: 730754 KB
- Manufacturer: ELPIDA [Elpida Memory]
- Click here to Download
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PD45128841-T Relative Products
PD45128841-I
The PD45128841-I ishigh-speed 134,217,728-bit synchronous dynamic random-access emories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs of PD45128841-I achieved high-speed data t...
PD45128441-T
The PD45128441-T is high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.The synchronous DRAMs of PD45128441-T achieved high-speed data ...
PD45128441-I
The PD45128441-I ishigh-speed 134,217,728-bit synchronous dynamic random-access emories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs of PD45128441-I achieved high-speed data t...
PD45128163-T
The PD45128163-T ishigh-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.The synchronous DRAMs of PD45128163-T achieved high-speed data t...
PD45128163-SU
The PD45128163-SU ishigh-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 2,097,152 × 16 × 4 (word × bit × bank).The synchronous DRAMs of PD45128163-SU achieved high-speed data transfer using the pipeline architecture.All inputs...
PD45128163-I
The PD45128163-I ishigh-speed 134,217,728-bit synchronous dynamic random-access emories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using th...
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