PDI1284P11

· Asynchronous operation
· 8-Bit transceivers
· 6 additional buffer/driver lines peripheral to cable
· 5 additional control lines from cable
· 5V tolerant
· ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
· Latch up protection exceeds 500 mA per JEDEC Std 19
· Input Hysteresis
· Low Noise Operation
· IEEE 1284 Compliant Level 1 & 2
· Overvoltage Protection on B/Y side for OFF-state
· A side 3-State option
· B side active or resistive pull up option
· Cable side VCC for 5V or 3V operation

NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4. V_OUT  B/Y (tr) guarantees only that this part will not be damaged by reflections in application so long as the voltage levels remain in the specified range.

The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit, bi-directional, parallel interface for personal computers. The part includes all 19 signal lines defined by the IEEE1284 interface specification for Byte, Nibble, EPP, and ECP modes. The part is designed for hosts or peripherals operating at 3.3V to interface 3.3V or 5.0V devices.

The PDI1284P11(A/B 1-8) allow data transmission from the A bus to the B bus, or from the B bus to the A bus, depending on the state of the direction pin DIR.

The PDI1284P11 has either totem pole or resistor pull up outputs, depending on the state of the high drive enable pin HD. The A bus has only totem pole style outputs. All inputs are TTL compatible with at least 400mV of input hysteresis at VCC  = 3.3V.