PECLDL

The PECLDL is designed for use with positive input pulses and will reproduce these at the output without inversion. On modules with delay change of 1 to 8ns/step, input impedance is approximately 900 ohms:on modules with delay change of 9ns/step and greater, input impedance is approximately 100 ohms. PECLDL can be driven by a standard ECL gate with an external pulldown resistor of 100 ohms to -2 V or 470 ohms to -5.2 V. Output is standard ECL10,000 single fan-in. These logic delay lines have the capability of driving up to 70 ECL DC loads.

PECLDL has many unique features: The first one is ECL input and output levels. The second one is delays stable and precise. The third one is 32-pin DIP package(.250 high). The forth one is it is available in delays up to 760ns. The fifth oen is it is available in 18 delays steps with resolution from 1 to 50ns. The sixth one is propagation delays fully compensated. The seventh one is all delays digitally programmable. The last one is 70 ECL DC fan-in capability.

There are some general specifications of PECLDL. Supply voltage is -5.2V±5% to Vee(can be operated on +5V to Vcc). Supply current is 135 mA typical. Logic 1 input at 25: voltage is -1.63 V max. Current is 265ua max.Logic 0 inpout at 25: Voltage is -1.63 V max. Current is .5 uA min. Logic 1 output at 25 is -.96 V min. Logic 0 output at 25 is -1.65 V max. Operating temperature range is -30 to +85. Storage temperature is -55 to +125.

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