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Part Number: PEEL18CV8Z

 

 

 

 

Description: The PEEL™18CV8Z is a Programmable Electrically Erasable Logic (PEEL™) SPLD (Simple Program...


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PEEL18CV8Z General Description


The PEEL™18CV8Z is a Programmable Electrically Erasable Logic (PEEL™) SPLD (Simple Programmable Logic Device) that features ultra-low, automatic "zero" power-down operation. The "zero power" (100 µA max. Icc) power-down mode makes the PEEL™18CV8Z ideal for a broad range of battery-powered portable equipment applications, from hand-held meters to PCM- CIA modems. EE-reprogrammability provides both the conve- nience of fast reprogramming for product development and quick product personalization in manufacturing, including Engineering Change Orders.

The PEEL™18CV8Z is logically and functionally similar to Anachip's 5 Volt PEEL™18CV8 and 3 Volt PEEL™18LV8Z. The differences between the PEEL™18CV8Z and PEEL™18CV8 include the addition of programmable clock polarity, a product term clock, and variable width product terms in the AND/OR Logic Array.

Like the PEEL™18CV8, the PEEL™18CV8Z is logical superset of the industry standard PAL16V8 SPLD. The PEEL™18CV8Z provides additional architectural features that allow more logic to be incorporated into the design. Anachip's JEDEC file translator allows easy conversion of existing 20 pin PLD designs to the PEEL™18CV8Z architecture without the need for redesign. The PEEL™18CV8Z architecture allows it to replace over twenty standard 20-pin DIP, SOIC, TSSOP and PLCC packages.

PEEL18CV8Z Maximum Ratings

Symbol
Parameter
Conditions
Rating
Unit
VCC
VO
IO
TST
TLT
Supply Voltage
Voltage Applied to Any Pin2
Output Current
Storage Temperature
Lead Temperature
Relative to Ground
Relative to Ground1
Per Pin (IOL, IOH)

Soldering 10 Seconds
-0.5 to +6.0
-0.5 to VCC +0.6
+25
-65 to +150
+300
V
V
mA

PEEL18CV8Z Features

Ultra Low Power Operation
- Vcc = 5 Volts ±10%
- Icc = 10 µA (typical) at standby
- Icc = 2 mA (typical) at 1 MHz
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Super set of standard PLDs
- Pin and JEDEC compatible with 16V8
- Ideal for use in power-sensitive systems
Architectural Flexibility
- Enhanced architecture fits in more logic
- 113 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear, Synchronous preset
- Independent output enables
- Programmable clock; pin 1 or p-term
- Programmable clock polarity
- 20 Pin DIP/SOIC/TSSOP and PLCC

PEEL18CV8Z Connection Diagram

PEEL18CV8Z  Connection Diagram

PEEL18CV8Z datasheet

PEEL18CV8Z
PDF/DataSheet Download

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